JPH02144922A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To realize high integration and a high speed and to enhance an electrical characteristic by a method wherein the surface of an emitter-electrode formation region of a silicon substrate is covered with a first insulating film as a substratum of a base-electrode formation layer, an undercut part is removed, a third insulating film is formed on a silicon film and the emitter- electrode formation region is etched. CONSTITUTION:A first insulating film 6 is formed on a main face of an epitaxial layer 2; a base-electrode formation layer 7A is formed on its whole upper face; a p-type impurity is introduced at a high concentration; a second insulating film 8 is formed on it. A patterning operation is executed; a base electrode 7 is formed. Then, the insulating film 6 exposed from the base electrode 7 is removed by an isotropic etching operation; the insulating film 6 formed under end parts of individual regions is removed by a side etching operation; undercut parts 9 are formed. Then, a silicon film 10 is formed on the whole surface of a substrate so as to fill the undercut parts 9; one part of the undercut parts 9 is removed; a third insulating film 11 is formed on the silicon film 10; only an amount corresponding to its film thickness is removed; an emitter electrode 14 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device having bipolar transistors or MI8FETQ.

[Conventional technology]

The technology described in "Nikkei Micro Devices J, November 1985 issue, pages 73 to 74," published by Nikkei McGraw-Hill, is an optimal technology for increasing the integration and speed of bipolar transistors.The bipolar transistor described in this technology The outline of the manufacturing method is as follows.

First, a silicon nitride film is formed on the main surface of an n-type epitaxial layer in a bipolar transistor formation region defined by an element isolation insulating film.

Next, a polycrystalline silicon film is formed on the silicon nitride film. Thereafter, the polycrystalline silicon film is patterned to form a space electrode so that the formation regions of the active space region and the emitter region are opened.

Next, boron (B), which is the Kp type impurity of the pace electrode,
will be introduced. Thereafter, using the silicon nitride film exposed from the formation regions of the active space region and the emitter region as an oxidation-resistant mask, the surface of the space electrode is oxidized to form a silicon oxide film.

Next, using the silicon oxide film on the surface of the pace electrode as an etching-resistant mask, the silicon nitride film on each formation region of the active pace region and emitter region is removed by etching, and the space electrode on the side of the removed region is etched. The silicon nitride film below the end portion is removed by side etching to form an undercut portion.

Next, a polycrystalline silicon film is deposited over the entire surface of the substrate so as to fill the undercut portion. After this, the polycrystalline silicon film deposited on the flat part excluding the undercut part is removed.
The epitaxial layer is removed by anisotropic etching such as active ion etching (hereinafter referred to as IE) to expose the surface of the epitaxial layer in the formation regions of the active space region and the emitter region.

Next, thermal oxidation is performed to form a silicon oxide film on a portion of the polycrystalline silicon film embedded in the undercut portion and on the surface of the exposed epitaxial layer.

Next, an n-type impurity is introduced into the main surface of the epitaxial layer in a region defined by the space electrode to form a p-type active base region. The external space region is formed by the n-type impurity introduced into the space electrode diffusing into the main surface of the epitaxial layer through the polycrystalline silicon film embedded in the undercut portion. The active pace region is connected to this external base region.

Next, after sequentially laminating a silicon oxide film and a polycrystalline silicon film on the entire surface of the substrate, these films are removed by anisotropic etching such as RIE, and an emitter opening is formed in the area defined by the pace electrode. do.

Next, a polycrystalline silicon film is formed so as to be connected to the active base region through the emitter opening, and the polycrystalline silicon film is patterned in a predetermined manner to form an emitter electrode. An n-type impurity is introduced into this emitter electrode, and this n-type impurity is introduced into this emitter electrode.
Type impurities are diffused into the active space region to form an n-type emitter region.

A bipolar transistor configured in this manner has the feature that it can be highly integrated because the external base region, active base region, emitter region, and emitter electrode can each be formed in self-alignment with respect to the space electrode. There is. In addition, in a bipolar transistor, the area where n-type impurities from the paste region diffuse is determined by the amount of side etching of the undercut portion under the space electrode and the amount of oxidation of a part of the polycrystalline silicon film buried in the undercut portion. Since the external base region is defined, it is possible to form a smaller external base region compared to the case where it is formed by photolithography technology, and has the feature that high integration can be achieved.

[Problem to be solved by the invention]

As a result of studying the method for manufacturing the above-mentioned bipolar transistor, the inventor found that the following problems occur.

In the conventional bipolar transistor, a polycrystalline silicon film is buried in the undercut portion at the end of the space electrode, and then the polycrystalline silicon film formed on each of the formation regions of the active base region and the emitter region is subjected to RIE, etc. It is removed by anisotropic etching. However, this anisotropic etching has a low etching selectivity between the polycrystalline silicon film and the epitaxial layer consisting of the single crystal silicon layer. In other words, the etching rate by RIE of the polycrystalline silicon film buried in the undercut portion and the single crystal silicon layer (epitaxial layer) in the region where the active paste and emitter are to be formed is almost the same. As a result, the surface of the epitaxial layer is considerably overetched in each of the active space region and the emitter region, so that the surface of the epitaxial layer is significantly roughened or damaged. As a result, crystal defects and dislocations occur on the surface of the epitaxial layer, causing destruction of the emitter-paste junction and carrier trapping. For these reasons, the cutoff frequency (fT) and current amplification factor (hpg) of the bipolar transistor decrease or become unbalanced.

Since such a problem occurs, the electrical characteristics of the bipolar transistor are deteriorated.

On the other hand, the present inventor considered forming a MISFET by applying a conventional bipolar transistor manufacturing method. Applying the bipolar transistor manufacturing method and structure to the MISFET manufacturing method and structure is advantageous in the following points. First, when a bipolar transistor and a MISFET are formed on the same semiconductor substrate, the manufacturing process can be made small (and the manufacturing cost can be small).

Second, the source/drain/diffusion layer of the MI 8 FET can be formed in a self-aligned manner with respect to the source/drain electrodes formed thereon and electrically connected.

For this reason, conventional MISFET formation techniques (for example, a technique of forming a source/drain diffusion layer, forming a contact hole by mask alignment, and forming a source/drain diffusion layer made of Al through the contact hole) Compared to the above, there is no need to estimate the margin due to mask alignment and enlarge the source/drain regions. Therefore, the junction capacitance between the source/drain region and the semiconductor substrate [(
Since the PN junction capacitance can be reduced, the speed of the MISFET can be increased.

In an attempt to obtain the first and second advantages described above, the present inventor developed a bipolar transistor manufacturing method and structure using MI.
The idea was to apply it to the manufacturing method and structure of SFET. However, the inventors have found that the following problems occur.

In the bipolar transistor, a polycrystalline silicon film is buried in the undercut portion at the end of the space electrode, and then the polycrystalline silicon film in the formation regions of the active space region and the emitter region is etched by anisotropic etching such as RIE. It is being removed. However, this anisotropic etching has a low etching selectivity between the polycrystalline silicon film and the epitaxial layer. In other words,"
The etching rate by IE of the polycrystalline silicon film buried in the undercut portion and the single crystal silicon layer (epitaxial layer) in the region where the active paste and emitter are to be formed are almost the same. As a result, the surface of the epitaxial layer in each of the active space region and the emitter region is considerably overetched, so that the surface of the epitaxial layer is significantly roughened or damaged. As a result, crystal defects and dislocations occur on the surface of the epitaxial layer, deteriorating the electrical characteristics of the bipolar transistor. That is, if the above-mentioned technique is simply applied to MISFET, the substrate surface (channel region) of the gate electrode formation region within the region defined by the source electrode and drain electrode corresponding to the space electrode will be roughened.
This causes deterioration of electrical characteristics such as variations in the threshold voltage Vth of SFET.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technology capable of achieving higher integration and higher speed, as well as improving electrical characteristics, in a semiconductor integrated circuit device having bipolar transistors.

Another object of the present invention is to provide a technique that can achieve the above object by reducing surface roughness of the emitter region of the bipolar transistor.

Another object of the present invention is to achieve higher integration and higher speed in a semiconductor integrated circuit device having MISFETs, and to
The object of the present invention is to provide a technology that can improve electrical characteristics.

Another object of the present invention is to provide a technique that can achieve the above object by reducing roughness or damage to the substrate surface of the gate electrode formation region of the MISFET. .

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief summary of the first invention among the inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device having a bipolar transistor, a first insulating film, a base electrode forming layer mainly composed of a silicon film containing impurities of a predetermined conductivity type, and a second insulating film are sequentially deposited on the main surface of a silicon substrate. and patterning the second insulating film and the pace electrode forming layer by anisotropic etching to form a pace electrode, and isotropically etching the first insulating film at the end of the base electrode on the emitter electrode forming region side. A silicon film is deposited over the entire surface of the substrate so as to bury the undercut, and the silicon film is thermally oxidized except for the undercut. An insulating film is formed, and this third
After removing the emitter electrode formation region of the insulating film by etching to expose the surface of the silicon substrate, a predetermined impurity is added to the silicon substrate using the 8g3 insulating film formed on the base electrode and its sidewalls as a mask. A silicon substrate is introduced onto the surface to form an intrinsic paste region, and then an emitter electrode is formed on the exposed surface of the silicon substrate.

Furthermore, an emitter region is formed by introducing a predetermined impurity into the exposed substrate through the emitter electrode.

Further, at the same time as the step of thermally oxidizing the silicon film except for the undercut portion to form an insulating film @3, impurities introduced in advance into the base electrode are added to the silicon film embedded in the undercut portion. An external paste region is formed by diffusing into the main surface of the silicon substrate through the silicon substrate.

Furthermore, among the inventions disclosed in this application, a brief outline of the second invention is as follows.

In a semiconductor integrated circuit device having MISF'ET,
A first insulating film, an electrode forming layer mainly composed of a silicon film having a conductivity type opposite to that of the silicon substrate, and a second insulating film are sequentially deposited on the main surface of a silicon substrate, and the second insulating film and the electrode are formed. The layer is patterned by anisotropic etching to form source electrodes and drain electrodes spaced apart from each other at predetermined intervals, and the ends of the source electrode, the drain N, and the ends of the poles on opposing sides are patterned. Side-etching each of the first insulating films by isotropic etching to form an undercut portion, depositing a silicon film over the entire surface of the substrate so as to bury the undercut portion, and removing the undercut portion. forming a third insulating film by thermally oxidizing the silicon film;
The third insulating film is etched away between the source electrode and the drain electrode to expose the surface of the silicon substrate, and a gate insulating film (fourth insulating film) is formed on the exposed surface of the silicon substrate.
In addition, in the same manufacturing process as the step of forming the third insulating film or in a subsequent process, a source is formed through the silicon film embedded in the undercut portion. The impurities introduced into each of the electrode and drain electrode are diffused into the main surface of the silicon substrate to form a source region and a drain region, respectively.

[Effect]

According to the above-described means of the first invention, when forming the base electrode by performing anisotropic etching (R, IE) on the base electrode forming layer, the first insulating film underlying the base electrode forming layer is etched. Since the surface of the pole formation region is coated with the emitter of the silicon substrate, it is possible to reduce roughening of the surface of the silicon substrate. Further, after the silicon film was formed as a third insulating film, excluding the undercut portion, the emitter electrode formation region of the third insulating film was removed by etching, so that there was a gap between the silicon substrate and the third insulating film. It is possible to increase the etching selectivity of the silicon substrate and reduce roughening of the surface of the emitter electrode forming region of the silicon substrate.

Furthermore, the size of the region where impurities are diffused from the base electrode can be determined by the amount of side etching of the fourth insulating film and the amount of formation of the third insulating film (thermal oxidation time), so the size of the external base region can be reduced. Therefore, high integration can be achieved.

Furthermore, since each of the intrinsic base region, external space region, emitter region, and emitter electrode can be formed in self-alignment with the base electrode, the area of the bipolar transistor can be reduced and high integration can be achieved. .

Furthermore, since the size of the external pace region can be reduced, the pn junction capacitance between the external pace region and the collector region can be reduced, and the operating speed can be increased.

Further, according to the means of the second invention described above, when performing anisotropic etching (roughly IE) on the electrode forming layer to form each of the source electrode and the drain electrode, the etching process is performed on the underlying electrode forming layer. Since the surface of the gate insulating film forming region of the silicon substrate is coated with the first insulating film, it is possible to reduce roughening of the surface of the silicon substrate. Furthermore, after forming a third insulating film by thermally oxidizing the silicon film, excluding the undercut portion, the gate electrode formation region of the third insulating film was removed by etching, so that the silicon substrate and the third insulating film were removed by etching. It is possible to increase the etching selectivity with respect to the insulating film and to reduce roughening of the surface of the gate insulating film forming region of the silicon substrate.

Further, the amount of side etching (undercut amount) of the first insulating film and the amount of formation of the third insulating film (amount of thermal oxidation of the silicon film) can be applied to the width of the north region and the drain region from the source electrode and the drain electrode, respectively. The source region,
The size of each drain region can be reduced and the degree of integration can be improved.

Further, since the pn junction capacitance between each of the source region and the drain region and the silicon substrate can be reduced, the operating speed can be increased.

Furthermore, since the source region, the drain region, and the gate electrode can be formed in self-alignment with respect to the source electrode and the drain electrode, the degree of integration can be improved.

〔Example〕

Hereinafter, the configuration of the present invention will be explained along with examples.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

(Example 1) Example I is an example of the first invention in which the present invention is applied to a semiconductor integrated circuit device having a bipolar transistor.

A bipolar transistor of a semiconductor integrated circuit device which is an embodiment of the first invention is shown in FIG. 1 (a sectional view of a main part).

As shown in FIG. 1, a bipolar transistor is constructed on the main surface of a silicon substrate. The silicon substrate is composed of a p-type semiconductor substrate 1 and an n-type epitaxial NI 2 grown on its main surface. In the bipolar transistor formation region, an n0 type semiconductor region (buried collector region) 3 is provided between the semiconductor substrate 1 and the epitaxial layer 2.

The bipolar transistor is defined by an isolation region composed of an element isolation insulating film 5, a p-type semiconductor region 4, and a semiconductor substrate 1, and is electrically isolated from other elements. The element isolation insulating film 5 is formed by oxidizing the epitaxial layer 2.

The semiconductor region 4 is the semiconductor substrate 1 under the element isolation insulating film 5.
and the epitaxial layer 2.

Bipolar transistors are mainly of the npn type, consisting of a collector region, a base region, and an emitter region.

The collector region is a semiconductor region (embedded collector region) 3
, an epitaxial layer 2, and an n+ type semiconductor region for potential raising (not shown). The semiconductor region for raising the potential is
A potential raising semiconductor region is defined by an element isolation insulating film 5 in a region different from the bipolar transistor forming region shown in FIG. 1, and is electrically connected to the semiconductor region 3. Although not shown, the collector region is configured such that a collector wiring is connected to the potential raising semiconductor region.

The heath area is an external heath area (graft bas area).
The p-type semiconductor region 12 is used as a p-type semiconductor region (also called
It is made up of a p-type semiconductor region 15 used as an aseregion. The semiconductor region 15, which is the active pace region, is the semiconductor region 1, which is the external pace region.
It is located in the center surrounded by 2. The semiconductor region 15, which is the active base region, is provided in electrical connection with the semiconductor region 12, which is the external space region. Each of the semiconductor regions 12 and 15 is provided on the main surface of the epitaxial layer 2.

The semiconductor region 12, which is an external space region, is electrically connected to the space electrode 7 with a silicon film 10 embedded in the undercut portion 9 interposed therebetween. The base electrode 7 is provided on the insulating film (first insulating film) 6 so as to surround the periphery of the semiconductor region 15, which is an active pace region, on one end side (inner side), and on the other end side (outer side) of the base electrode 7. is the element isolation insulating film 5
It is pulled out at the top of the. The base electrode 7 is made of a polycrystalline silicon film doped with an n-type impurity (for example, B) that reduces resistance. The silicon film 10 is made of, for example, a polycrystalline silicon film. A pace wiring 19 is connected to the upper surface of the base electrode 7 through a connection hole 18 formed in an insulating film (second insulating film) 8 formed on the pace electrode 7 and an interlayer insulating film 17 . The base wiring 19 is formed of, for example, an aluminum film or an aluminum alloy film to which copper or silicon is added.

The emitter region is composed of an n-type semiconductor region 16. The semiconductor region 16 is a main part of the semiconductor region 15 within a region defined by the base electrode 7 and an insulating film (a part of the third insulating film, also referred to as a sidewall spacer) 11 formed on the sidewall of the base electrode 7. It is configured on the surface. An emitter electrode 14 is electrically connected to the semiconductor region 16 through a contact hole (emitter opening) 13 whose region is defined by the insulating film 11 . The emitter electrode 14 is, for example, n
It is composed of a polycrystalline silicon film into which type impurities (arsenic or phosphorus) are introduced. The emitter electrode 14 and the base electrode 7 are connected to the PACE 1! An insulating film 8 (second insulating film) provided on the top of the pole 7 and an insulating film 11 formed on the side wall of the base electrode 7
Each part is electrically isolated. Emitter electrode 1
4 is connected to an emitter wiring 19 through a connection hole 18 formed in an interlayer insulating film 17. Emitter wiring 1
9 is made of the same conductive material as the base wiring 19 and the collector wiring (not shown).

Next, the method for manufacturing the above-mentioned bipolar transistor will be briefly explained using FIGS. 2 to 9 (cross-sectional views of main parts shown for each manufacturing process).

First, as shown in FIG. 2, a p-type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, n-type impurities are introduced into the main surface of the semiconductor substrate 1 in the bipolar transistor formation region. Thereafter, n-type impurities are introduced into the main surface of the semiconductor substrate 1 between the bipolar transistor formation regions.

Next, a 1cn-type epitaxial layer 2 is grown on the main surface of the semiconductor substrate 1 to form a silicon substrate.

In the step of growing the epitaxial layer 2, the introduced n-type impurity is stretched and diffused to form the + type semiconductor region 3, and at the same time, the introduced n-type impurity is stretched and diffused. A p medium semiconductor region 4 is formed.

Next, between the bipolar transistor forming regions, the main surface of the epitaxial layer 2 is selectively oxidized to form an element isolation insulating film 5. The element isolation insulating film 5 is formed to such an extent that it contacts the semiconductor region 4 .

Next, in the bipolar transistor formation region, an absolute R film (first insulating film) 6 is formed on the main surface of the epitaxial layer 2. The insulating film 6 is formed of a silicon oxide film obtained by oxidizing the main surface of the epitaxial layer 2, and has a thickness of about 400 to 600 (A). This isolation film 6 mainly electrically isolates the epitaxial layer 2 and a base electrode (7) that will be formed in a later step, and also serves as an etching stopper layer when patterning the pace electrode (7). Use as.

Next, as shown in FIG. 3, seven base electrode forming layers are formed over the entire surface of the substrate including the upper part of the insulating film 6. The base electrode forming layer 7A is formed by, for example, normal pressure (approximately 1.0 (torr)) CVD (Chemical VaperDepo)
It is formed from a polycrystalline silicon film deposited by
Formed with a film thickness of about 2500 to 3500 (A"l).

Note that the pace electrode forming layer 7A is a silicide film in which a high melting point metal film is formed on top of a polycrystalline silicon film, or a silicide film in which a high melting point metal silicide film is laminated on top of a polycrystalline silicon film.
It may be formed of a composite film mainly composed of a polycrystalline silicon film.

Next, a p-type impurity (for example, B) is introduced into the pace electrode forming layer 7A at a high concentration to reduce the resistance value of the pace electrode forming layer 7A.

Next, an insulating film (second
An insulating film) 8 is formed. The insulating film 8 is formed of a silicon oxide film deposited by CVD, for example, and has a film thickness of 2000 to 3000 (
It is formed with a film thickness of about A).

Next, as shown in FIG. 4, a predetermined pattern is applied to the insulating film 8 and the pace electrode forming layer 7A to form the pace electrode 7. This patterning is performed in step 5 to remove the base electrode formation M7 on each formation region of the active base region and emitter region of the bipolar transistor. Patterning improves the processing accuracy of the pace electrode 7,
Moreover, anisotropic etching such as RIE is performed so that the side wall of the pace electrode 7 has a steep stepped shape. Anisotropic etching is performed on the insulating film (second insulating film) 8, base electrode formation N
7A can be sequentially overlapped and cut. As the etching gas, for example, CHF or CF is used.

When performing this anisotropic etching, the pace electrode forming layer 7
The insulating film 6 formed on the base of A is used as an etchant and a barrier layer. This insulating film 6 protects the surface of the epitaxial layer 2 made of single-crystal silicon in regions where the active base region and emitter region are formed.

Next, as shown in FIG. 5, the insulating film 6 exposed from the pace electrode 7 is etched and removed by isotropic etching, and the edges of the active base region, emitter region, and emitter electrode formation region side of the pace electrode 7 are removed. The insulating film 6 formed under the part is also removed by side etching, and the undercut part 9 is removed.
form.

The undercut portion 9 is formed to have a side etching amount of about 1000 (A) in the lateral direction (direction parallel to the substrate 1) from the end of the pace electrode 7, for example. For example, hydrofluoric acid is used as the isotropic etching solution.

Next, as shown in FIG. 6, a silicon film 10 is formed over the entire surface of the substrate so as to bury the undercut portion 9. The silicon film 10 is formed of a polycrystalline silicon film deposited by low pressure (approximately 0.3 torr or less) CVD. The silicon film 10 is formed to have a thickness of, for example, about 200 to 300 Å so that the undercut portion 9 can be substantially completely buried. According to the results of basic research by the inventor, low-pressure CV
The polycrystalline silicon film deposited in step D can be reliably embedded inside the undercut portion 9 formed in a minute size as described above. The silicon film 10 embedded in the undercut portion 9 is connected to the lower surface of the pace electrode 7.

Next, as shown in FIG. 7, the silicon film 10 is replaced with an insulating film (
(third insulating film) 11 (or changed). The insulating film (third insulating film) IIFi is formed of a silicon oxide film obtained by thermally oxidizing the entire surface of the silicon film 10. Specifically, a portion of the silicon film 10 embedded in the undercut portion 9 extends approximately 200 mm from the side wall of the pace electrode 7 in the lateral direction (parallel to the substrate).
~300 [A] is formed in the insulating film 11.

Through the thermal oxidation process for forming this insulating film 11, the seventh
As shown in the figure, the n-type impurity introduced into the space electrode 7 is diffused into the main surface of the epitaxial layer 2 through the silicon film 10 remaining in the undercut portion 9. As a result, a p-type semiconductor region 12 is formed which is used as the external base region of the bipolar transistor. The amount of sand etching of the insulating film (first insulating film) 6 and the amount of oxidation required to form part of the silicon film 10 embedded in the undercut portion 9 formed by the side etching into the insulating film 11 are used to form the space electrode 7. The size of the region (approximately 700 to 800 [A] in the lateral direction) in which the n-type impurity is diffused is defined. For this reason, the semiconductor region 1 used as an external base region
2 can be formed with a size considerably smaller than the minimum processing size using photolithography technology. Semiconductor region 12, which is this external base region, can be formed in self-alignment with respect to space electrode 7. Note that this is not limited to the thermal oxidation step for forming the semiconductor region 12Fi, which is the external base region, and the insulating film 11, but also for the subsequent heat treatment step, for example, the same heat treatment step as the step for forming the active space region and the emitter region, or a further subsequent heat treatment step. It may be formed in a separate process.

Next, as shown in FIG. 8, there is an active pace region.

In each of the emitter region and the emitter electrode formation region, the insulating film 11 is removed by an amount corresponding to the film thickness to form a connection hole 13, and then the epitaxial layer 2 in the region where the insulating film 11 is removed is removed. A p-type semiconductor region 15 is formed on the main surface to be used as an active space region.

The insulating film 11 is removed by anisotropic etching such as IE etching. By using this anisotropic etching, a portion of the insulating film 11 used as a sidewall spacer can remain on the sidewall portion of the space electrode 7. The remaining insulating film 11 (and a part (sidewall spacer)) is formed in self-alignment with the pace electrode 7. Since this insulating film 11 is formed using the silicon film 10, it is not aligned with the pace electrode 7. It is possible to eliminate the step of newly depositing an insulating film for electrically separating the emitter 1!pole H formed in a later step.In addition, the remaining part of the insulating film 11
The film thickness can be easily controlled by the amount of anisotropic etching, and the film thickness is several thousand [
It can be formed with a film thickness as thin as A].

Furthermore, since the insulating film 11 is formed of a silicon oxide film (SIO), the etching selectivity with respect to the epitaxial layer (Si) 2 can be increased during anisotropic etching of the insulating film 11. . The etching selectivity is, for example, f
Jl'sio, :5i=10:1 mark. Therefore, roughness or damage to the surface of the epitaxial layer 2 can be reduced during the removal of the insulating film 11 in each of the active space region, emitter region, and emitter electrode formation region.

The semiconductor region 15, which is the active pace axis region, can be formed by introducing n-type impurities into the main surface of the epitaxial layer 2 by ion implantation. Since this n-type impurity is introduced into the region defined by the space electrode 7 and the insulating film 11 remaining on its sidewall, that is, into the connection hole 13, the semiconductor region 15 is formed in self-alignment with the space electrode 7. .

Next, as shown in FIG. 9, an emitter electrode 14 is formed so as to be electrically connected to the semiconductor region 15, which is an active space region, through the connection hole 13.

After this, an n+ type semiconductor region 16 to be used as an emitter region is formed.

The emitter electrode 14 is formed of a polycrystalline silicon film deposited by normal pressure CVD, and the semiconductor region 16 which is the emitter region is doped with an n-type impurity, for example, on the main surface of the semiconductor region 15 through the entire emitter electrode 14. Formed by introducing type impurities. Further, the semiconductor region 16 may be formed by diffusing an n-type impurity introduced into the emitter electrode 14 into the semiconductor region 15.

In this manner, in the semiconductor integrated circuit device ffi having a bipolar transistor, the base electrode forming layer 7A is formed mainly of a silicon film with an insulation @ (first insulating film) 6 interposed on the main surface of the silicon substrate (1, 2). After sequentially depositing the insulating film 8 and the insulating film 8, when patterning the pace electrode forming layer 7A and the insulating film 8 by anisotropic etching to form the base electrode 7, the insulating film underlying the pace electrode forming layer 7A is Since the surface of the emitter/base formation region of the silicon substrate (epitaxial layer 2) is exposed in step 6, roughening of the surface of the epitaxial layer 2 can be reduced. Further, the silicon film 10 is removed by etching, except for at least a part of the undercut portion 9, and the insulating film 11 in the insulating film (third insulating film) and the mitter/pace forming region is removed, so that the silicon substrate (epitaxial layer 2) Since the etching selectivity between the silicon substrate and the insulating film 11 is large, roughening of the surface of the emitter paste forming region of the silicon substrate (epitaxial layer 2) can be reduced. As a result, the electrical characteristics of the bipolar transistor can be improved.

The p-type impurity is diffused from the space electrode 7 by the amount of side etching of the insulating film (first insulating film) 6 and the amount of the insulating film 11 formed at the undercut portion (oxidation '!i of the silicon film 10). Since the size of the region can be defined, the size of the semiconductor region 12, which is the external base region, can be reduced,
High integration can be achieved.

Further, the semiconductor region 12 which is the external space region, the semiconductor region 15 which is the active base region. Semiconductor region 16, which is an emitter region. Since each of the emitter electrodes 14 can be formed in self-alignment with respect to the base electrode 7, the area of the bipolar transistor can be reduced by an amount corresponding to the mask alignment allowance in the manufacturing process, and high integration can be achieved. Can be done.

Furthermore, since the semiconductor region 12, which is the external space region, can be formed in a small size only in a portion of the undercut portion 9, the pn junction capacitance with the epitaxial layer 2, which is the collector region, can be reduced. Therefore, the operating speed of the bipolar transistor can be increased.

Semiconductor region 16 which is the emitter region shown in FIG.
After the step of forming, an interlayer insulating film 17 and a connection hole 18 are sequentially formed as shown in FIG.

Next, emitter wiring 19. A base wiring 19 and a collector wiring are formed. By performing these series of manufacturing steps, the semiconductor integrated circuit device of Example I is completed.

When configuring a semiconductor integrated circuit for the purpose of increasing the operating speed, it is desirable to configure the circuit only with bipolar transistors, but it is not limited to this. It may also be composed of types.

Further, in the present invention, instead of the element isolation insulating film 5, a trench-type inlay region formed by forming a brocade on a semiconductor substrate may be used. In this case, the base electrode 7
Since the MIS capacitance i between the layer and the epitaxial layer 20 can be reduced compared to when the element isolation insulating film 5 is used, furthermore,
Bipolar transistors can be made faster.

Note that the present invention is not limited to npn-type bipolar transistors, but can be applied to pnp-type bipolar transistors. In this case, the first invention can mainly reduce surface roughness of the collector region.

[Example ■]

Example (2) is an example of the second invention in which the present invention is applied to a semiconductor integrated circuit device having MI8B'I,T.

kj of the semiconductor integrated circuit device which is the embodiment of the second invention
I 8 F E '1'' is shown in FIG. 10 (section g section).

It is constructed on the main surface of the board. The silicon substrate includes a p-type semiconductor substrate 1 and an n-type well region 20 formed on its main surface.
It is made up of.

The region of MISFETFi is defined by an element isolation insulating film 21, and is electrically isolated from other elements. The element isolation insulating film 21 is formed by oxidizing the main surface of the well region 20.

MISFET is mainly used in one well region 20. Gate insulating film 24. Gate electrode 26. It is composed of a pair of p+ type semiconductor regions 23 which are a source region and a drain region. In other words, the MISFET is a p-channel MISFET.

Well region 20 is used as a channel forming region.

Semiconductor region which is the source region 23V! , a source electrode (
S) 22. Similarly, the semiconductor region 23 which is a drain region is connected to the drain electrode (to) 22 with the silicon film 10 buried in the undercut 99 interposed therebetween. One end of each of the source electrode 22 and the drain electrode 22 is provided on the insulating film (first insulating film) 6, and the other end is drawn out above the element isolation insulating film 21.

1 source electrode 22 similar to the pace electrode 7 of Example I
, the drain electrodes 22 are each made of a polycrystalline silicon film into which p-type impurities are introduced to reduce the resistance value. The other end of the source electrode 22 is connected to the source wiring @2 through the connection hole 18.
7, and the other end side of the drain electrode 22 is connected to the connection hole 18.
It is connected to a drain wiring 27 (not shown) through the drain wiring 27 (not shown). Each of the source wiring 27 and drain wiring 27 (not shown) is formed of, for example, an aluminum film or an aluminum alloy film containing copper or silicon.

The gate electrode 26 is connected to the source electrode 22 . Drain electrode 22
, and an insulating film formed on their sidewalls (third insulating film)
A gate insulating film (fourth insulating film) 24 is provided on the main surface of the well region 20 in a region defined by 11, that is, in the connection hole 25. The gate electrode 26 is made of, for example, a polycrystalline silicon film doped with n-type impurities (AS or P). The gate electrode 26 has a connecting hole 1
A gate wiring 27 is connected through the entirety of the gate line 8.

Next, regarding the method for manufacturing the above-mentioned MISFET, the 11th
This will be briefly explained using FIG. 18 (a sectional view of the main part shown for each mold making process).

First, as shown in FIG. 11, a p-
A type semiconductor substrate 1 is prepared.

Next, in the MISFET formation region, an n-type well region 20 is formed on the main surface of the semiconductor substrate 1 to form a silicon substrate.

Next, between the MISFET formation regions, the well region 2
0 is selectively oxidized to form an element isolation insulating film 21.

Next, an insulating film (first insulating film) 6 is formed on the main surface of the well region 20 in the MISFET formation region defined by the element isolation insulating film 21 . Insulating film 6
Similarly to the insulating film 6 of Example (2), the well region 20 is
and a source electrode and a drain electrode (22) to be formed later.
It is used as an etching stopper layer when patterning the source and drain electrodes (22).

Next, as shown in FIG. 12, an electrode formation layer (source and drain electrode formation layer) is formed on the entire surface of the substrate including the upper part of the insulating film 6.
22A is formed. The electrode forming layer 22A is made of, for example, normal pressure C.
It is formed from a polycrystalline silicon film deposited by VD.

Next, a high concentration of p-type impurities is introduced into the electrode forming layer 22AK to reduce its resistance value.

Next, an insulating film (second insulating film) 8 is formed on the entire upper surface of the electrode forming layer 22A.

Next, as shown in FIG. 13, the insulating film 8 and the electrode forming layer 22A are subjected to predetermined patterning to form a source electrode (S) 22 and a drain electrode (D) 22. This patterning is performed on the gate electrode formation area! This is done so as to remove the roughly formed layer 22A. Patterning is RI
This is done using anisotropic etching such as E.

When performing this anisotropic etching, the electrode forming layer is used as a stopper layer, and this insulating film 6 protects the surface of the well region 200 in the gate electrode forming region.

Next, as shown in FIG. 14, the source electrode (8) 22,
The insulating film (first insulating film) 6 exposed within the region defined by each of the drain electrodes 22 is etched and removed by isotropic etching, and the insulating film 6 formed at the ends of the source/drain electrodes 22 is removed. The etched insulating film 6 is removed by side etching to form an undercut portion 9.

Next, as shown in FIG.
A silicon film 10 is formed over the entire surface of the substrate so as to embed it. The silicon film 10 is formed of a polycrystalline silicon film deposited by low pressure (approximately 0.3 torr or less) CVD.

Next, as shown in FIG. 16, the silicon film 10 is formed (changed) into an insulating film (third insulating film) 11 except for at least a portion of the undercut portion 9. The insulating film 11 is formed on the entire surface of the silicon film 10 by a thermal oxidation process to form the insulating film 11, as shown in FIG. The p-type impurity introduced into each of the drain electrodes 22 passes through the silicon film 1o remaining in the undercut portion 9. The p+ type semiconductor regions 23 are diffused into the main surface of the well region 20 to form a pair of p+ type semiconductor regions 23 serving as a source region and a drain region.

Next, as shown in FIG. 17, in the gate electrode formation region, the insulating film (third insulating film) 11 is removed by an amount corresponding to the film thickness, and the channel region 20 of the MISFET is removed.
After exposing the surface of the well region 20 in the region A,
Apart from the removed insulating film 11 on the channel region,
A gate insulating film (fourth insulating film) is formed on the main surface of the well region 20.
Form 24. The gate insulating film 24 is located in the well region 2o.
The main surface is formed of an oxidized silicon oxide film, and
It is formed with a film thickness of about [A].

The insulating film 11 is removed by anisotropic etching such as RIE. By using this anisotropic etching, the source electrode 22. A portion of the insulating film 11 used as a sidewall spacer can remain on each sidewall of the drain electrode 22.

Further, as in the above-mentioned Example I, the insulating film 11F! Since it is formed of a silicon oxide film, the etching selectivity with respect to the well region (single crystal silicon region) 20 can be increased during anisotropic etching.

Therefore, in the gate electrode formation region, the insulating film 11
Upon removal, roughness on the surface of the well region 20 can be reduced.

Next, as shown in FIG. 18, a gate electrode 26 is formed through the entire connection hole 25 on the main surface of the well region 20 with a gate insulating film 24 interposed therebetween. The gate electrode 26 is formed of, for example, a polycrystalline silicon film deposited by atmospheric pressure CVD, and is doped with n-type impurities (for example, P or As).

As described above, the second invention provides a semiconductor integrated circuit device having a MISFET, in which an insulating film 6 is interposed on the main surface of a silicon substrate (1°20), and an electrode forming layer 22A mainly composed of a silicon film is formed. This electrode forming layer 22AK was deposited, and impurities having a four-hole shape opposite to that of the silicon substrate (well region 20) were introduced, and this electrode forming layer 22A was patterned by anisotropic etching, so that the electrode forming layer 22A was separated from each other at a predetermined interval. Source electrode (
S) Form each of the 22° drain electrodes (D) 22, and side-etch the insulating film 6 at the end of the source electrode 22 and the end of the drain electrode 22 facing each other by isotropic etching. , an undercut portion 9 is formed, a silicon film 10 is deposited over the entire surface of the substrate so as to bury this undercut portion 9, and the silicon film 10 is deposited on an insulating film 11 except for a portion of the undercut portion 9. The insulating film 11 between the source electrode 22 and the drain electrode l electrode 22 is removed by etching to expose the surface of the silicon substrate (4).
A step of forming a gate electrode 26 on the exposed surface of the silicon substrate with a gate insulating film 24 interposed therebetween is provided. !
Further, the second invention is a method for forming the silicon film 10 embedded in at least a portion of the undercut portion 9 in the same manufacturing process as the process of forming the insulating film 11 or in a process subsequent to the process of forming the insulating film 11.
Throughout the source electrode 22. It also includes a step of diffusing into the main surface of the drain plate (2) to form a pair of semiconductor regions 23, each serving as a source region and a drain region. According to the manufacturing method of the present invention, the electrode forming layer 22A is anisotropically etched to form the source electrode 22. When forming each of the drain electrodes 22, since the surface of the gate insulating film forming region of the silicon substrate (2) is covered with the insulating film 6 underlying the electrode forming layer 22A, the surface is prevented from becoming rough. At the same time, after forming the silicon film 10 on the insulating film 11 and removing a part of the undercut portion 9, the gate electrode formation region of this insulating film 11 was removed by etching, so that the silicon substrate (a) and Since the etching selectivity with respect to the insulating film 11 is high, roughening of the surface of the gate insulating film formation region of the silicon substrate can be reduced.

Also, depending on the amount of side etching of the insulating film (first insulating film) 6 and the amount of forming of the insulating film 11 in the undercut portion (oxidation i of the silicon film 10), the source electrode 22° and the drain electrode 22
Since the size of the region in which the impurities forming the pair of semiconductor regions 23 which are the source region and the drain region are diffused can be defined from each of the above, the size of the semiconductor region 23 can be reduced and M The degree of integration can be improved.

Furthermore, since the pn junction capacitance between the pair of semiconductor regions 23, which are the source and drain regions, and the silicon substrate 2 can be reduced, the operating speed of the MISFET can be increased.

Further, a pair of semiconductor regions 23. which are the source region and the drain region. Each of the gate electrodes 26 is connected to the source electrode 22
．． Since it can be formed in self-alignment with each of the drain electrodes 22, the degree of integration of the MISFET can be improved by the amount corresponding to the mask alignment allowance in the manufacturing process.

After the step of forming the gate electrode 26 shown in FIG. 18, the glabella insulating film 17 is formed as shown in FIG. The connection holes 18 are sequentially formed, and then the source wirings 27 . A drain wiring a (not shown) and a gate wiring 27 are each formed.

The male side ■ semiconductor integrated circuit device is completed.

Note that the present invention is not limited to p-channel M 18 FET, but can be applied to n-channel MISFET.

Further, the present invention may constitute a mixed type semiconductor integrated circuit device in which the bipolar transistor of the embodiment I and the MISPET of the embodiment (2) are combined.

In this case, the step of forming the pace electrode 7 and the step of forming the source electrode 2
2 and the drain electrode 22, many manufacturing steps can be made common.

Furthermore, the present invention can also be applied to a 7jBi-CMOS device in which a bipolar transistor, a P-channel MISFET, and a H-channel MISFET are mounted together on the same semiconductor substrate. FIG. 19 shows an example in which the present invention is applied to Bs-0MO8.

A method for manufacturing the B1-CMOS device shown in FIG. 19 will be briefly described.

As shown in FIG.
By a well-known technique, an n+ type buried layer 3. After forming the p+ type buried layer 4 in a required region, an epitaxial layer made of single crystal silicon is formed on the entire surface of the semiconductor substrate 1, and then selective impurity ion implantation and diffusion techniques are used. A P-type inlation region 4A in the epitaxial layer.

A P-type well region 4B and an N-type well region 20 are respectively formed. Furthermore, the surface of the epitaxial layer is selectively thermally oxidized to form an element isolation insulating film 5.

The P-type isolation shoulder region 4A, the p''-type buried layer 4.
By the p-type semiconductor substrate 1 and the element isolation insulating film 5,
Bipolar transistor formation region and M I S F E
The T forming regions are electrically isolated. After forming the element isolation insulating film 5, an n+ type collector potential drawing region 300 is formed in the n well region 20 of the bipolar transistor forming region by selective ion implantation and diffusion of n type impurities (for example, phosphorus). Form.

The subsequent manufacturing steps can be easily accomplished by combining Example (2) and Example (2) of the present invention. For example, the pace electrode 7 and the P-channel MISFE
T source/drain electrode 22 and N channel type MISF
It is possible to form the source/drain electrodes 22A of the ET using a polycrystalline silicon film formed in the same process. In this case, the pace electrode 7 and the source/drain 1! ! P-type impurities are ion-implanted into the pole 22, and n-type impurities are ion-implanted into the source/drain electrodes 22AKH.

In this case, the P-type and N-type impurities are selectively implanted, so one additional photomask is required. Furthermore, the emitter electrode 14 and the P-channel type MISF
E '1'' gate electrode 26 and N channel type M I
The gate electrode 26 of SF''E'l' can also be formed using a polycrystalline silicon film formed in the same process.

Also, the number of photomasks increases by -, but the gate electrode of the P-channel type MI8FET and the N-channel type MI
It is also possible to change the conductivity type of the gate electrode of the SFET by each MI-on implant with a predetermined threshold voltage.

20 and 21 are plan views of essential parts of the Hi-0MO8 bipolar transistor region and P-channel MISFET region shown in FIG. 19.

As shown in FIG. 20, the bipolar transistors are laid out.

To make the drawing easier to understand, insulating films other than the element isolation insulating film 5 are not shown. As shown in the figure, the pace electrode 7Vi is formed to surround the emitter region 16 (n+). The pace potential is supplied by the wiring layer 9 through a connection hole (paste C0NT) formed on the base electrode 7. Emitter' [Q
14 is formed so that a portion thereof overlaps with the pace electrode 7. The emitter potential is emitter potential 14
Through the connection hole (emitter C0NT) formed on the top,
It is supplied by the wiring layer 19. The n-type collector potential extraction region 300 also has a contact hole (corrupted). According to the layerer HC of such a bipolar transistor, the base electrode 7 has an emitter region 16 (n+), an external space region 12 (ri) ).

It will be understood that the intrinsic space region 1s(p) and the emitter electrode 14 can be formed in a self-aligned manner. It may also be formed on the base electrode 7 on the side opposite to the space C0NTVi.

As shown in FIG. 21, the P-channel MI SFE'l
"H, it's laid out.

Similarly to FIG. 20, insulating films other than the element isolation insulating film 5 are not shown.

As shown in the figure, a source electrode 22 (S) and a drain electrode 22□□□ are formed facing each other so as to sandwich a gate electrode 26 therebetween. The source electrode 22 (S) and the drain electrode 22 (D> have connection holes, (source C0
NT, drain C0NT), wiring layer 27°27
A is connected. Source/drain electrode 822 (S
), 22) is formed in a self-aligned manner by diffusion of P-type impurities from the electrode. A strain region 23(1)+) is formed in each of the regions. A part of the gate electrode 26 has a source/drain voltage ff122 (
S) and 22 (to) are formed in an overlapping manner. on the gate electrode 26.

A wiring layer 27 is formed through the connection hole (gate C0NT). The connection between the gate electrode 26 and the wiring layer 27 does not have to be made on the active region surrounded by the element isolation insulating film 5. In this case, the gate electrode 26 is further extended in the Y direction, and the gate electrode 26 is placed on the element isolation insulating film 5.
6 and the wiring layer 27 are connected. In addition, the P-type impurity is N
It is possible to form an N-channel MISFET shown in FIG. 19 by simply changing the type impurity. It goes without saying that the present invention is not limited to the above embodiments, and may be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

The first invention and second invention disclosed in this application are as follows.

According to the first invention, in a semiconductor integrated circuit device having a bipolar transistor, it is possible to achieve higher integration and faster operation speed, and also to reduce surface roughness of the emitter region and improve electrical characteristics. be able to.

According to the second invention, in a semiconductor integrated circuit device having a MISFET, it is possible to achieve higher integration and higher operating speed, and also to reduce roughness of the substrate surface in the gate electrode formation region and improve electrical characteristics. can be improved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a main part showing a bipolar transistor of a semiconductor integrated circuit device which is an embodiment of the first invention, and FIGS. 2 to 9 show the bipolar transistors shown in FIG. FIG. 10, which is a cross-sectional view of the main parts shown for each step, is an MI of a semiconductor integrated circuit device that is an embodiment of the second invention.
The main part cross-sectional views of the SFET, FIGS. 11 to 18, are as follows:
FIG. 10 is a cross-sectional view of the main parts of MI 8 FET shown in each manufacturing process, and FIG. -CMO
FIG. 2 is a sectional view of a main part of the S device. FIG. 20 is a plan view of the main part of the bipolar region of the B*-cMOS device shown in FIG. 19, and FIG. 21 is a P-channel type MI of the B1-CMOS device shown in FIG. 19.
FIG. 3 is a plan view of a main part of a 5FET region. In the figure, 1... Semiconductor substrate, 2... Epitaxial layer, 3.4, 12, 15.16... Semiconductor region, 6, 8
゜11... Insulating film, 7... Space electrode, 9... Undercut portion, 10... Silicon film, 14... Emitter electrode, 20... Well region, 22... Source electrode Or drain electrode, 23...semiconductor region, 24...
- Gate insulating film, 26... Gate electrode, 300...
Collector draw-out area, C0NT...connection hole. 1 (ρ-J

Claims (1)

[Claims] 1. In a bipolar transistor that draws out an emitter electrode from within a region surrounded by a base electrode, a) forming a base electrode mainly composed of a silicon film with a first insulating film interposed on the main surface of a silicon substrate; b) anisotropically etching the base electrode forming layer;
c) side-etching the first insulating film at the end of the emitter electrode formation region surrounded by the base electrode by isotropic etching to form an undercut portion; and d) depositing a silicon film over the entire surface of the silicon substrate so as to bury the undercut, and e) forming the silicon film as a third insulating film except for a part of the undercut. f) removing the emitter formation region of the third insulating film by etching to expose the surface of the silicon substrate; and g) forming an emitter electrode on the exposed surface of the silicon substrate. A method of manufacturing a semiconductor integrated circuit device, comprising: 2. An impurity of a predetermined conductivity type is introduced into the base electrode, and the impurity introduced into the base electrode is diffused into the main surface of the silicon substrate through the silicon film embedded in the undercut portion, thereby leaving the external base region. 2. A method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising: forming a semiconductor integrated circuit device. 3. The semiconductor according to claim 2, wherein the external base region is defined by diffusion of impurities from the base electrode, and is formed in self-alignment with the base electrode. A method of manufacturing an integrated circuit device. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the silicon film embedded in the undercut portion is a polycrystalline silicon film deposited by low-pressure CVD. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein anisotropic etching is used for etching the emitter electrode formation region of the third insulating film. 6. The base electrode and the emitter electrode are electrically separated by a third insulating film remaining on the sidewall of the base electrode when the third insulating film is etched by anisotropic etching. A method for manufacturing a semiconductor integrated circuit device according to claim 5. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein each of the first insulating film and the third insulating film is a silicon oxide film. 8. The active base region of the bipolar transistor is:
The emitter region is formed by introducing impurities of a predetermined conductivity type into the main surface of the silicon substrate in the region surrounded by the base electrode, and the emitter region is formed by introducing an emitter into the main surface of the silicon substrate in the region surrounded by the base electrode. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed by introducing an impurity of a predetermined conductivity type through an electrode. 9. In a semiconductor integrated circuit device including a MISFET, a) step of sequentially forming an electrode formation layer mainly composed of a silicon film and a second insulating film with a first insulating film interposed on the main surface of a silicon substrate, and b) c) patterning the electrode forming layer by anisotropic etching to form a source electrode and a drain electrode separated from each other at a predetermined interval; and d) side-etching the first insulating film at the end of the source electrode and the end of the drain electrode on sides facing each other by isotropic etching to form an undercut part. e) depositing a silicon film over the entire surface of the silicon substrate so as to bury the undercut; and f) depositing the silicon film on a third insulating film except for a part of the undercut. g) removing the space between the source electrode and the drain electrode of the third insulating film by etching to expose the surface of the silicon substrate; and h) forming a gate insulator on the exposed surface of the silicon substrate. a step of forming a gate electrode with a film interposed therebetween, and a step of forming a gate electrode through the silicon film embedded in the undercut portion in the same manufacturing step as the step of forming the third insulating film or in a subsequent step. , the impurities introduced into each of the source and drain electrodes are diffused into the main surface of the silicon substrate,
1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of forming each of a source region and a drain region. 10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein the silicon film embedded in the undercut portion is a polycrystalline silicon film deposited by low-pressure CVD. 11. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein the etching of the gate electrode formation region of the third insulating film uses anisotropic etching. 12. The electrical separation between each of the source electrode and drain electrode and the gate electrode is controlled by the third
Claim 11, characterized in that when the insulating film is etched by anisotropic etching, the third insulating film remaining on the side walls of each of the source electrode and the drain electrode is etched.
A method for manufacturing a semiconductor integrated circuit device as described in 1. 13. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein each of the first insulating film and the third insulating film is a silicon oxide film.