JPH0412027B2 - - Google Patents

Info

Publication number
JPH0412027B2
JPH0412027B2 JP1093259A JP9325989A JPH0412027B2 JP H0412027 B2 JPH0412027 B2 JP H0412027B2 JP 1093259 A JP1093259 A JP 1093259A JP 9325989 A JP9325989 A JP 9325989A JP H0412027 B2 JPH0412027 B2 JP H0412027B2
Authority
JP
Japan
Prior art keywords
chip
substrate
space
polymer
coating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1093259A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0216756A (ja
Inventor
Jooji Amiin Josefu
Resurii Butsuchiwarutaa Suteibun
An Kobatsuku Kyarorin
Jon Parumaa Maikeru
Adamusu Hoo Peiji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH0216756A publication Critical patent/JPH0216756A/ja
Publication of JPH0412027B2 publication Critical patent/JPH0412027B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10W74/47—
    • H10W72/30—
    • H10W74/012—
    • H10W74/131—
    • H10W74/15—
    • H10W74/473—
    • H10W72/07331—
    • H10W72/856—
    • H10W90/724—
    • H10W90/734—

Landscapes

  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP1093259A 1988-05-02 1989-04-14 パツケージ構造体 Granted JPH0216756A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US18927788A 1988-05-02 1988-05-02
US189277 1988-05-02

Publications (2)

Publication Number Publication Date
JPH0216756A JPH0216756A (ja) 1990-01-19
JPH0412027B2 true JPH0412027B2 (cg-RX-API-DMAC10.html) 1992-03-03

Family

ID=22696665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1093259A Granted JPH0216756A (ja) 1988-05-02 1989-04-14 パツケージ構造体

Country Status (2)

Country Link
EP (1) EP0340492A3 (cg-RX-API-DMAC10.html)
JP (1) JPH0216756A (cg-RX-API-DMAC10.html)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4999699A (en) * 1990-03-14 1991-03-12 International Business Machines Corporation Solder interconnection structure and process for making
US5121190A (en) * 1990-03-14 1992-06-09 International Business Machines Corp. Solder interconnection structure on organic substrates
US5390082A (en) * 1992-07-06 1995-02-14 International Business Machines, Corp. Chip carrier with protective coating for circuitized surface
US5249101A (en) * 1992-07-06 1993-09-28 International Business Machines Corporation Chip carrier with protective coating for circuitized surface
US5783867A (en) * 1995-11-06 1998-07-21 Ford Motor Company Repairable flip-chip undercoating assembly and method and material for same
JPH09214111A (ja) * 1996-01-30 1997-08-15 Matsushita Electric Ind Co Ltd 電子回路基板
US5894173A (en) * 1996-11-27 1999-04-13 Texas Instruments Incorporated Stress relief matrix for integrated circuit packaging
US5760337A (en) * 1996-12-16 1998-06-02 Shell Oil Company Thermally reworkable binders for flip-chip devices
US5726391A (en) * 1996-12-16 1998-03-10 Shell Oil Company Thermosetting Encapsulants for electronics packaging
US6238948B1 (en) * 1999-03-03 2001-05-29 Intel Corporation Controlled collapse chip connection (C4) integrated circuit package that has a fillet which seals an underfill material
US6528345B1 (en) * 1999-03-03 2003-03-04 Intel Corporation Process line for underfilling a controlled collapse
US20020014688A1 (en) * 1999-03-03 2002-02-07 Suresh Ramalingam Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials
US6331446B1 (en) * 1999-03-03 2001-12-18 Intel Corporation Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state
US6538210B2 (en) 1999-12-20 2003-03-25 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module, radio device having the same, and method for producing the same
US6700209B1 (en) 1999-12-29 2004-03-02 Intel Corporation Partial underfill for flip-chip electronic packages
JP2002110715A (ja) * 2000-10-04 2002-04-12 Sony Corp 半導体装置の製造方法
JP4637809B2 (ja) * 2001-06-15 2011-02-23 株式会社リコー 半導体装置、画像読取ユニット及び画像形成装置
EP1283547A1 (en) * 2001-07-31 2003-02-12 United Test Center Inc. Packaging process for semiconductor package
US6597061B1 (en) 2001-08-03 2003-07-22 Sandisk Corporation Card manufacturing technique and resulting card

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2929339A1 (de) * 1978-07-24 1980-02-14 Citizen Watch Co Ltd Halbleiteranordnung
JPS58107641A (ja) * 1981-12-21 1983-06-27 Seiko Keiyo Kogyo Kk 半導体装置の封止方法
JPS60147140A (ja) * 1984-01-11 1985-08-03 Hitachi Ltd 半導体素子チツプの実装方法
CA1226966A (en) * 1985-09-10 1987-09-15 Gabriel Marcantonio Integrated circuit chip package

Also Published As

Publication number Publication date
EP0340492A2 (en) 1989-11-08
EP0340492A3 (en) 1990-07-04
JPH0216756A (ja) 1990-01-19

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