JPH0410346U - - Google Patents
Info
- Publication number
- JPH0410346U JPH0410346U JP1990050897U JP5089790U JPH0410346U JP H0410346 U JPH0410346 U JP H0410346U JP 1990050897 U JP1990050897 U JP 1990050897U JP 5089790 U JP5089790 U JP 5089790U JP H0410346 U JPH0410346 U JP H0410346U
- Authority
- JP
- Japan
- Prior art keywords
- joined
- parts
- lead frame
- inner lead
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の電子部品用リードフレームの
第１の実施例に係る構成を示す平面図、第２図は
第１図のＢ−Ｂ線に係る断面図、第３図は第１の
実施例の電子部品用リードフレームに半導体素子
が配設された状態を示す断面図、第４図ａ，ｂは
第２の実施例の構成を示す断面図、第５図は第３
の実施例の構成を示す断面図、第６図は従来の技
術に係る電子部品用リードフレームの平面図、第
７図は第６図に係るＡ−Ａ線断面図である。
１１……タブ部、１１ａ，１１ｂ，１１ｃ，１
１ｄ……突起部位、１２……インナーリード部、
１２ａ，１２ｂ……インナーリード、１３……導
電性接着剤、１４……半導体素子、１５ａ，１５
ｂ……配線ワイヤ。
FIG. 1 is a plan view showing the structure of the first embodiment of the lead frame for electronic components of the present invention, FIG. 2 is a sectional view taken along line B-B in FIG. 1, and FIG. A sectional view showing a state in which a semiconductor element is arranged on a lead frame for an electronic component according to an embodiment, FIGS. 4a and 4b are sectional views showing the configuration of a second embodiment, and FIG.
FIG. 6 is a plan view of a lead frame for electronic components according to the prior art, and FIG. 7 is a cross-sectional view taken along the line A--A in FIG. 6. 11...Tab portion, 11a, 11b, 11c, 1
1d...Protrusion part, 12...Inner lead part,
12a, 12b... Inner lead, 13... Conductive adhesive, 14... Semiconductor element, 15a, 15
b...Wiring wire.
Claims (1)
インナーリードとを備え、 前記部品配設部位の接合位置の周囲に、接合さ
れる部品方向に突出した突起部位が設けられるこ
とを特徴とする電子部品用リードフレーム。[Scope of claim for utility model registration] At least the parts where the parts are joined,
A lead frame for an electronic component, comprising: an inner lead, and a protruding portion protruding in the direction of the components to be joined is provided around the joining position of the component placement region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990050897U JPH0410346U (en) | 1990-05-16 | 1990-05-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990050897U JPH0410346U (en) | 1990-05-16 | 1990-05-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0410346U true JPH0410346U (en) | 1992-01-29 |
Family
ID=31569846
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990050897U Pending JPH0410346U (en) | 1990-05-16 | 1990-05-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0410346U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54159532U (en) * | 1978-04-27 | 1979-11-07 | ||
| WO2013018485A1 (en) * | 2011-08-01 | 2013-02-07 | 株式会社三井ハイテック | Lead frame, method for manufacturing lead frame and semiconductor device using same |
-
1990
- 1990-05-16 JP JP1990050897U patent/JPH0410346U/ja active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54159532U (en) * | 1978-04-27 | 1979-11-07 | ||
| WO2013018485A1 (en) * | 2011-08-01 | 2013-02-07 | 株式会社三井ハイテック | Lead frame, method for manufacturing lead frame and semiconductor device using same |
| JP2013033822A (en) * | 2011-08-01 | 2013-02-14 | Mitsui High Tec Inc | Lead frame, manufacturing method of lead frame, and semiconductor device using lead frame |
| CN103718291A (en) * | 2011-08-01 | 2014-04-09 | 株式会社三井高科技 | Lead frame, method for manufacturing lead frame and semiconductor device using same |