JPH0385660U - - Google Patents

Info

Publication number
JPH0385660U
JPH0385660U JP14740089U JP14740089U JPH0385660U JP H0385660 U JPH0385660 U JP H0385660U JP 14740089 U JP14740089 U JP 14740089U JP 14740089 U JP14740089 U JP 14740089U JP H0385660 U JPH0385660 U JP H0385660U
Authority
JP
Japan
Prior art keywords
bonding area
bonded
wiring
pattern
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14740089U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14740089U priority Critical patent/JPH0385660U/ja
Publication of JPH0385660U publication Critical patent/JPH0385660U/ja
Pending legal-status Critical Current

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Landscapes

  • Solid State Image Pick-Up Elements (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案にかかる基板の平面図、第2図
は本考案にかかる端子部領域の平面図、第3図は
本考案にかかるボンデイング領域の平面図である
。 1……基板、2……端子部領域、3……ボンデ
イング領域、4……位置決めマーク、5……外部
接続端子、7……センサチツプ、14……切断部
FIG. 1 is a plan view of a substrate according to the present invention, FIG. 2 is a plan view of a terminal region according to the present invention, and FIG. 3 is a plan view of a bonding region according to the present invention. DESCRIPTION OF SYMBOLS 1... Board, 2... Terminal area, 3... Bonding area, 4... Positioning mark, 5... External connection terminal, 7... Sensor chip, 14... Cutting part.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] センサチツプを複数個、順次隣接して並べ、ボ
ンデイングを行うマルチツプリニアイメージセン
サに使用する基板において、該基板は外部接続端
子を具備した配線パターンが形成された端子部領
域とセンサチツプがボンデイングされる配線パタ
ーンとが形成されたボンデイング領域からなり、
該ボンデイング領域の配線パターンは同一のパタ
ーンを少なくとも2個以上繰り返して形成され前
記基板をボンデイング領域の所定の位置で切断す
るための位置決めマークが形成されていることを
特徴とする実装基板の構造。
In a substrate used for a multi-tipped linear image sensor in which a plurality of sensor chips are arranged adjacent to each other and bonded, the substrate has a terminal area where a wiring pattern with external connection terminals is formed and wiring to which the sensor chips are bonded. consisting of a bonding area formed with a pattern,
A structure of a mounting board characterized in that the wiring pattern in the bonding area is formed by repeating at least two identical patterns, and a positioning mark for cutting the board at a predetermined position in the bonding area is formed.
JP14740089U 1989-12-20 1989-12-20 Pending JPH0385660U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14740089U JPH0385660U (en) 1989-12-20 1989-12-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14740089U JPH0385660U (en) 1989-12-20 1989-12-20

Publications (1)

Publication Number Publication Date
JPH0385660U true JPH0385660U (en) 1991-08-29

Family

ID=31693914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14740089U Pending JPH0385660U (en) 1989-12-20 1989-12-20

Country Status (1)

Country Link
JP (1) JPH0385660U (en)

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