JPH0382059A - 樹脂封止型半導体装置 - Google Patents

樹脂封止型半導体装置

Info

Publication number
JPH0382059A
JPH0382059A JP1218984A JP21898489A JPH0382059A JP H0382059 A JPH0382059 A JP H0382059A JP 1218984 A JP1218984 A JP 1218984A JP 21898489 A JP21898489 A JP 21898489A JP H0382059 A JPH0382059 A JP H0382059A
Authority
JP
Japan
Prior art keywords
semiconductor element
resin
lead frame
thin metal
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1218984A
Other languages
English (en)
Inventor
Kenji Ooyanai
賢治 大谷内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1218984A priority Critical patent/JPH0382059A/ja
Publication of JPH0382059A publication Critical patent/JPH0382059A/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止型半導体装置に関する。
〔従来の技術〕
従来、半導体素子搭載部のないリードフレームを用いた
樹脂封止型半導体装置は次のようになっていた。
すなわち、半導体素子と半導体素子搭載部のないリード
フレームの内部リードを金属細線にて接続した後、半導
体素子及びリードフレームの内部リードを封止用樹脂に
て封止する構造となっていた。
〔発明が解決しようとする課題〕
上述した従来の樹脂封止型半導体装置では、半導体素子
を保持するのが、半導体素子と半導体素子搭載部のない
リードフレームの内部リードヲ接続する金属細線のみで
あるため、半導体素子及びリードフレームの内部リード
な封止用樹脂にて封止する際、半導体素子は樹脂に押し
流されやすく、前記金属細線が引っ張られ、切断したり
、あるいは半導体素子の上部角の部分に金属細線が触れ
、電気的に短絡してしまうなどの欠点がある。
また、金属細線が引っ張られた対辺では金属細線がたる
み、金属細線どうし、あるいは金属細線と該金属細線と
絶縁されているべき内部リードが短絡してしまうという
欠点もある。
また、従来の封止用樹脂は、半導体素子の基板であるシ
リコン結晶との密着性が悪いため、赤外線リフローなど
の熱衝撃を加えるとシリコン結晶が露出している半導体
素子の裏面と封止樹脂との間にすき間ができ、そのすき
間が拡大していき、封止樹脂の外部まで達してしまい、
耐湿性を悪くするという欠点がある。
〔課題を解決するための手段〕
本発明の樹脂封止型半導体装置は、半導体素子搭載部の
ないリードフレームを用いた樹脂封止型半導体装置にお
いて、半導体素子と半導体素子搭載部のないリードフレ
ームの内部リードを金属細線にて接続した後、前記半導
体素子と、前記リードフレームの内部リードとの空隙の
一部をポツティング樹脂にて埋め半導体素子を、内部リ
ードに固定し、その後封止用樹脂にて樹脂封止すること
を特徴とするものである。
〔実施例〕
次に、本発明について図面を参照して説明する。
第１図（ａ）〜（ｃ）は、本発明の第１の実施例の上面
図、Ａ−Ａ’線断面図及びＢ　Ｊ　Ｂ　’線断面図であ
る。
半導体素子ｌは、第１図に示すように半導体素子搭載部
のないリードフレーム２の内部リード２゜と金属細線３
により接続されており、さらに半導体素子１は、半導体
素子の搭載部のないリードフレーム２の内部リード２．
と半導体素子１の４隅でポッティング樹脂４により固定
されている。
この半導体素子１の周囲は、全てポッティング樹脂４に
より覆われている。
このような構造にすることに依り封止用樹脂５により、
封止する際に半導体素子１が移動することを防ぎ、金属
細線３が変形することが防止できる。
また、熱衝撃により封止樹脂５に割れが発生することも
防止することができる。
第２図（ａ）、　（ｂ）は本発明の第２の実施例のＡ−
Ａ’線断面図及びＢ−Ｂ’線断面図である。
半導体素子１は裏面をシリコン酸化膜あるいは半導体素
子１の回路形成面を被覆しているガラス状保護膜などの
膜６により覆われている。
半導体素子ｌの裏面の膜６は、封止用樹脂５との密着性
が良いため、熱衝撃により封止用樹脂５に割れが発生す
ることも防止できる。
さらにこの実施例では半導体素子１の裏面をポッティン
グ樹脂で覆う必要がないため、封止用樹脂５の厚さを０
．３〜０．５ｍｍ薄くできるという利点も合せ持つ。
〔発明の効果〕
以上説明したように本発明によれば、半導体素子と半導
体素子搭載部のないリードフレームの内部リードを金属
細線にて接続した後、前記半導体素子と前記リードフレ
ームの内部リードとの空隙の一部をポッティング樹脂に
て埋め、半導体素子をリードフレームの内部リードに固
定し、その後封止用樹脂にて封止する際、半導体素子が
封止用樹脂によって押し流されることを防止し、しかも
金属細線が引っ張られ、切断したり、あるいは半導体素
子上部角の部分に金属細線が触れ、電気的に短絡したり
、あるいは金属細線どうし″、あるいは金属細線と該金
属細線と絶縁されているべき内部リードが短絡してしま
うことを防止できる効果がある。
また、熱衝撃により、封止用樹脂に割れが発生すること
を防止し、信頼性を向上させる効果も合せ持つ。
【図面の簡単な説明】
第１図（ａ）〜（ｃ）は本発明の第１の実施例の上面図
、Ａ−Ａ’線断面図及びＢ−Ｂ’線断面図、第２図（ａ
）、　（ｂ）は本発明の第２の実施例のＡ−Ａ’線断面
図及びＢ−Ｂ’線断面図である。 １・・・・・・半導体素子、２・・・・・・半導体素子
搭載部のないリードフレーム、２ｉ・・・・・・内部リ
ード、３・・・・・・金属細線、４・・・・・・ポツテ
ィング樹脂、５・・・・・・封止用樹脂、６・・・・・
・ガラス状膜。 （ α ） （ｂ） 第 図

Claims (1)

    【特許請求の範囲】
  1. 半導体素子搭載部のないリードフレームを用いた樹脂封
    止型半導体装置において、半導体素子と半導体素子搭載
    部のないリードフレームの内部リードは金属細線にて接
    続されており、前記半導体素子と前記リードフレームの
    内部リードとの空隙の少くとも一部がポッティング樹脂
    より埋められていて、半導体素子をリードフレームの内
    部リードに固定し、さらに前記半導体装置、金属細線、
    内部リード及びポッティング樹脂を封止用樹脂で封止す
    ることを特徴とする樹脂封止型半導体装置。
JP1218984A 1989-08-24 1989-08-24 樹脂封止型半導体装置 Pending JPH0382059A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1218984A JPH0382059A (ja) 1989-08-24 1989-08-24 樹脂封止型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1218984A JPH0382059A (ja) 1989-08-24 1989-08-24 樹脂封止型半導体装置

Publications (1)

Publication Number Publication Date
JPH0382059A true JPH0382059A (ja) 1991-04-08

Family

ID=16728446

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1218984A Pending JPH0382059A (ja) 1989-08-24 1989-08-24 樹脂封止型半導体装置

Country Status (1)

Country Link
JP (1) JPH0382059A (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0547818A (ja) * 1991-08-09 1993-02-26 Sharp Corp 半導体装置
US5605863A (en) * 1990-08-31 1997-02-25 Texas Instruments Incorporated Device packaging using heat spreaders and assisted deposition of wire bonds
US5847467A (en) * 1990-08-31 1998-12-08 Texas Instruments Incorporated Device packaging using heat spreaders and assisted deposition of wire bonds
US6383841B2 (en) * 1998-03-12 2002-05-07 Delta Electronics, Inc. Method for encapsulating with a fixing member to secure an electronic device
US6818968B1 (en) * 2000-10-12 2004-11-16 Altera Corporation Integrated circuit package and process for forming the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5605863A (en) * 1990-08-31 1997-02-25 Texas Instruments Incorporated Device packaging using heat spreaders and assisted deposition of wire bonds
US5847467A (en) * 1990-08-31 1998-12-08 Texas Instruments Incorporated Device packaging using heat spreaders and assisted deposition of wire bonds
JPH0547818A (ja) * 1991-08-09 1993-02-26 Sharp Corp 半導体装置
US6383841B2 (en) * 1998-03-12 2002-05-07 Delta Electronics, Inc. Method for encapsulating with a fixing member to secure an electronic device
US6818968B1 (en) * 2000-10-12 2004-11-16 Altera Corporation Integrated circuit package and process for forming the same

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