JPH0376507B2 - - Google Patents

Info

Publication number
JPH0376507B2
JPH0376507B2 JP25298084A JP25298084A JPH0376507B2 JP H0376507 B2 JPH0376507 B2 JP H0376507B2 JP 25298084 A JP25298084 A JP 25298084A JP 25298084 A JP25298084 A JP 25298084A JP H0376507 B2 JPH0376507 B2 JP H0376507B2
Authority
JP
Japan
Prior art keywords
input
processing
output
output device
status information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP25298084A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61131148A (ja
Inventor
Kyo Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PFU Ltd
Original Assignee
PFU Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PFU Ltd filed Critical PFU Ltd
Priority to JP25298084A priority Critical patent/JPS61131148A/ja
Publication of JPS61131148A publication Critical patent/JPS61131148A/ja
Publication of JPH0376507B2 publication Critical patent/JPH0376507B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP25298084A 1984-11-30 1984-11-30 入出力装置制御方式 Granted JPS61131148A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25298084A JPS61131148A (ja) 1984-11-30 1984-11-30 入出力装置制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25298084A JPS61131148A (ja) 1984-11-30 1984-11-30 入出力装置制御方式

Publications (2)

Publication Number Publication Date
JPS61131148A JPS61131148A (ja) 1986-06-18
JPH0376507B2 true JPH0376507B2 (enrdf_load_stackoverflow) 1991-12-05

Family

ID=17244825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25298084A Granted JPS61131148A (ja) 1984-11-30 1984-11-30 入出力装置制御方式

Country Status (1)

Country Link
JP (1) JPS61131148A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS61131148A (ja) 1986-06-18

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