JPH0369180B2 - - Google Patents

Info

Publication number
JPH0369180B2
JPH0369180B2 JP60123172A JP12317285A JPH0369180B2 JP H0369180 B2 JPH0369180 B2 JP H0369180B2 JP 60123172 A JP60123172 A JP 60123172A JP 12317285 A JP12317285 A JP 12317285A JP H0369180 B2 JPH0369180 B2 JP H0369180B2
Authority
JP
Japan
Prior art keywords
layer
conductivity type
cmos
diffusion layer
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60123172A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61281545A (ja
Inventor
Yutaka Yoshida
Yoshihiro Shigeta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP60123172A priority Critical patent/JPS61281545A/ja
Publication of JPS61281545A publication Critical patent/JPS61281545A/ja
Publication of JPH0369180B2 publication Critical patent/JPH0369180B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP60123172A 1985-06-06 1985-06-06 バイポ−ラ・ｃｍｏｓ半導体装置 Granted JPS61281545A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60123172A JPS61281545A (ja) 1985-06-06 1985-06-06 バイポ−ラ・ｃｍｏｓ半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60123172A JPS61281545A (ja) 1985-06-06 1985-06-06 バイポ−ラ・ｃｍｏｓ半導体装置

Publications (2)

Publication Number Publication Date
JPS61281545A JPS61281545A (ja) 1986-12-11
JPH0369180B2 true JPH0369180B2 (enrdf_load_stackoverflow) 1991-10-31

Family

ID=14853964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60123172A Granted JPS61281545A (ja) 1985-06-06 1985-06-06 バイポ−ラ・ｃｍｏｓ半導体装置

Country Status (1)

Country Link
JP (1) JPS61281545A (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198374A (en) * 1990-04-03 1993-03-30 Oki Electric Industry Co., Ltd. Method of making biCMOS integrated circuit with shallow N-wells
JPH03286562A (ja) * 1990-04-03 1991-12-17 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
KR100190008B1 (ko) * 1995-12-30 1999-06-01 윤종용 반도체 장치의 정전하 보호 장치

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58216455A (ja) * 1982-06-09 1983-12-16 Toshiba Corp 半導体装置の製造方法
JPS59188162A (ja) * 1983-11-29 1984-10-25 Ricoh Co Ltd 半導体集積回路装置

Also Published As

Publication number Publication date
JPS61281545A (ja) 1986-12-11

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