JPH0368195A - Laminated ceramic board and manufacture thereof - Google Patents

Laminated ceramic board and manufacture thereof

Info

Publication number
JPH0368195A
JPH0368195A JP1203642A JP20364289A JPH0368195A JP H0368195 A JPH0368195 A JP H0368195A JP 1203642 A JP1203642 A JP 1203642A JP 20364289 A JP20364289 A JP 20364289A JP H0368195 A JPH0368195 A JP H0368195A
Authority
JP
Japan
Prior art keywords
layer
conductor
ceramic
alumina
melting point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1203642A
Other languages
Japanese (ja)
Other versions
JPH0828577B2 (en
Inventor
Takashi Nagasaka
崇 長坂
Hideki Nakagawara
中川原 英樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP1203642A priority Critical patent/JPH0828577B2/en
Priority to DE4024612A priority patent/DE4024612C2/en
Publication of JPH0368195A publication Critical patent/JPH0368195A/en
Priority to US08/007,020 priority patent/US5290375A/en
Publication of JPH0828577B2 publication Critical patent/JPH0828577B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B9/00Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B9/00Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00
    • B32B9/005Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00 comprising one layer of ceramic material, e.g. porcelain, ceramic tile
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00Layered products comprising a layer of metal
    • B32B15/20Layered products comprising a layer of metal comprising aluminium or copper
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B9/00Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00
    • B32B9/04Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00 comprising such particular substance as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B9/041Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00 comprising such particular substance as the main or only constituent of a layer, which is next to another layer of the same or of a different material of metal
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2250/00Layers arrangement
    • B32B2250/40Symmetrical or sandwich layers, e.g. ABA, ABCBA, ABCCBA
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00Properties of the layers or laminate
    • B32B2307/20Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
    • B32B2307/202Conductive
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00Properties of the layers or laminate
    • B32B2307/20Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
    • B32B2307/206Insulating
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00Properties of the layers or laminate
    • B32B2307/30Properties of the layers or laminate having particular thermal properties
    • B32B2307/306Resistant to heat
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2311/00Metals, their alloys or their compounds
    • B32B2311/02Noble metals
    • B32B2311/06Platinum
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2311/00Metals, their alloys or their compounds
    • B32B2311/02Noble metals
    • B32B2311/08Silver
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2311/00Metals, their alloys or their compounds
    • B32B2311/12Copper
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2311/00Metals, their alloys or their compounds
    • B32B2311/22Nickel or cobalt
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2315/00Other materials containing non-metallic inorganic compounds not provided for in groups B32B2311/00 - B32B2313/04
    • B32B2315/02Ceramics
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2315/00Other materials containing non-metallic inorganic compounds not provided for in groups B32B2311/00 - B32B2313/04
    • B32B2315/08Glass
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00Electrical equipment

Landscapes

  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To improve insulation between conductors in reliability even if pinholes occur at the burning of a ceramic layer by a method wherein an insulating layer, which is burnable at a temperature lower than the lowest temperature at which the ceramic layer can be burned, is formed on the surface of the ceramic layer. CONSTITUTION:An alumina printed layer 4a, to which an opening is provided so as to expose a part of a high melting metal inner conductor 3, is formed, and a via-fill conductor layer 5 of high melting point metal conductor is formed in the opening so as to be electrically connected to the inner conductor 3. In the same manner as above, an alumina printed layer 4b, a via-fill conductor 5b, and an alumina printed layer 4c are successively formed. A high melting point metal inner conductor 6 is formed into a prescribed pattern, an alumina printed layer 7a, a via-fill conductor layer 8a, an alumina printed layer 7b,... are successively formed, and a glass printed layer 9 is formed on the uppermost layer 7c. By this setup, even if defects such as pinholes or the like occur in the alumina printed layers 7a, 7b, and 7c, the glass printed layer 9 gets into the defects concerned to prevent a ceramic laminated board of this design from decreasing in insulation.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、セラミック層と高融点金属導体層とを交互に
積層形成し、この高融点金属導体層に電気接続して導体
層を形成してなるセラミック積層基板に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention comprises forming a ceramic layer and a high melting point metal conductor layer alternately, and electrically connecting the high melting point metal conductor layer to form a conductor layer. This invention relates to a ceramic laminate substrate.

〔従来の技術〕[Conventional technology]

この種のセラミック積層基板の形成プロセスとして、種
々のプロセスが開発されている。そのうち、多層化に適
するものとして、グリーンシート法がよく用いられてお
り、さらにこのグリーンシ−ト法は印刷積層法とシート
積層法に分けられる。
Various processes have been developed to form this type of ceramic multilayer substrate. Among these, the green sheet method is often used as a method suitable for multilayering, and the green sheet method is further divided into a printing lamination method and a sheet lamination method.

特に印刷積層法は、シート積層法と比較して各セラミッ
ク層の膜厚が薄いために寄生容量が大きくなることを利
用してコンデンサを内蔵した回路用基板等に用いられる
In particular, the printing lamination method is used for circuit boards with built-in capacitors, etc., taking advantage of the fact that the thickness of each ceramic layer is thinner than that of the sheet lamination method, resulting in a larger parasitic capacitance.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところで、この印刷積層法は、内層導体を印刷形成した
後で、例えばアル旦ナベーストを3層程度印刷し、−括
焼成する。そして、このアルミナペースト印刷時にゴミ
・ホコリ、スキージゴム粉、空気等による異物が混入す
ると、基板焼成時にこの異物も焼成されて、アル逅す層
にピンホール等の欠陥を生ずることが明らかとなった。
By the way, in this printing lamination method, after printing and forming the inner layer conductor, for example, about three layers of aluminum base paste are printed and then fired. It has become clear that if foreign matter such as dirt, dust, squeegee rubber powder, or air gets mixed in when printing this alumina paste, this foreign matter will also be fired during the substrate firing process, causing defects such as pinholes in the alumina layer. .

この欠陥は後工程で基板表面へ形成される厚膜導体と内
層導体間を短絡する可能性を生じさせるものであり、絶
縁信頼性を低下させる原因となり、問題である。
This defect poses a problem because it may cause a short circuit between the thick film conductor formed on the surface of the substrate and the inner layer conductor in a later process, which causes a decrease in insulation reliability.

そこで、本発明は上記の問題点に鑑みなされたものであ
り、各導体間の絶縁信頼性を向上することを目的として
いる。
Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to improve the insulation reliability between each conductor.

〔課題を解決するための手段〕[Means to solve the problem]

上記の目的を達成するために、本発明のセラミック積層
基板は、セラミック層と該セラミック層の焼成可能な最
低温度より高い融点を有する高融点金属導体層とが交互
に積層形成され、かつ、前記高融点金属導体層に電気接
続して導体層を形成してなるセラミック積層基板におい
て、前記セラミック層の焼成可能な最低温度より低温度
にて焼成可能な絶縁層を前記セラミック層の表面上に形
成したことを特徴としている。
In order to achieve the above object, the ceramic laminate substrate of the present invention has a ceramic layer and a high melting point metal conductor layer having a melting point higher than the lowest firing temperature of the ceramic layer, and In a ceramic laminated substrate formed by electrically connecting to a high melting point metal conductor layer to form a conductor layer, an insulating layer that can be fired at a temperature lower than the lowest temperature at which the ceramic layer can be fired is formed on the surface of the ceramic layer. It is characterized by what it did.

また、本発明のセラミック積層基板の製造方法は、セラ
ミック層と該セラミック層の焼成温度より高い融点を有
する高融点金属導体層とを交互に積層形成し、これを同
時に所定の焼成温度にて焼成する工程と、 前記セラミック層の表面上に絶縁層を形成し、この絶縁
層を前記焼成温度より低温度にて焼成する工程と、 前記絶縁層の上に、前記高融点金属導体層に電気接続す
るように導体層を形成する工程とを備えることを特徴と
している。
Further, the method for manufacturing a ceramic multilayer substrate of the present invention involves alternately laminating ceramic layers and high melting point metal conductor layers having a melting point higher than the firing temperature of the ceramic layers, and simultaneously firing them at a predetermined firing temperature. forming an insulating layer on the surface of the ceramic layer and firing the insulating layer at a temperature lower than the firing temperature; and electrically connecting the high melting point metal conductor layer on the insulating layer. The method is characterized by comprising a step of forming a conductor layer so as to do so.

〔作用〕[Effect]

上記のように構成することにより、セラミック層と高融
点金属導体層との焼成時にセラミック層に仮にピンホー
ル等の欠陥が生じたとしても、この上から絶縁層を形成
し、焼成することによりその欠陥を塞ぐことができる。
With the above structure, even if defects such as pinholes occur in the ceramic layer during firing of the ceramic layer and the high-melting point metal conductor layer, the insulating layer is formed on top of this and fired. Defects can be plugged.

その結果、絶縁層上に形成される導体層と高融点金属導
体層との間は完全に絶縁されるようになり、絶縁信頼性
が向上する。
As a result, the conductor layer formed on the insulating layer and the refractory metal conductor layer are completely insulated, improving insulation reliability.

〔実施例〕〔Example〕

以下、本発明を図面に示す実施例を用いて説明する。第
1図は本発明の一実施例の断面構造を示している。図に
おいて、1はアルミナテープであり、このアル累ナテー
ブ1内にはスルーホール2が形成され、W(タングステ
ン)あるいはM。
Hereinafter, the present invention will be explained using embodiments shown in the drawings. FIG. 1 shows a cross-sectional structure of an embodiment of the present invention. In the figure, numeral 1 is an alumina tape, and a through hole 2 is formed in the alumina tape 1, which is made of W (tungsten) or M.

(モリブデン)等の高融点金属導体が埋められている。A high melting point metal conductor such as (molybdenum) is buried.

アルミナテープ1上には所定パターンの高融点金属導体
層から成る内層導体3が形成される。
An inner layer conductor 3 made of a refractory metal conductor layer having a predetermined pattern is formed on the alumina tape 1.

そして、この上に内層導体3の一部が露出するように開
口したアルξす印刷層4aが形成され、その開口部には
さらに高融点金属導体層から成るビアフィル導体層5a
が内層導体に電気接続するようにして形成される。同様
にして、その上にはアル逅す印刷層4b、ビアフィル導
体層5bおよびアル逅す印刷層4cが順次形成される。
Then, a printed layer 4a having an opening such that a part of the inner layer conductor 3 is exposed is formed thereon, and a via fill conductor layer 5a made of a high melting point metal conductor layer is further formed in the opening.
is formed in such a way that it is electrically connected to the inner layer conductor. Similarly, an aluminum-containing printed layer 4b, a via-fill conductor layer 5b, and an aluminum-containing printed layer 4c are sequentially formed thereon.

そして、その上に高融点金属導体層から成る内層導体6
が所定パターンに形成され、さらにアルξす印刷層7a
、ビアフィル導体層8a、アルミナ印刷層7b、ビアフ
ィル導体層8b、アルミナ印刷層7c及びビアフィル導
体層8cが順次積層形成される。
Then, an inner layer conductor 6 made of a high melting point metal conductor layer is provided thereon.
is formed in a predetermined pattern and further includes a printed layer 7a
, via-fill conductor layer 8a, alumina print layer 7b, via-fill conductor layer 8b, alumina print layer 7c, and via-fill conductor layer 8c are sequentially laminated.

最上層のアル稟す印刷層7c上にはガラス印刷層9が形
成される。また、最上層のビアフィル導体層8cと厚膜
導体11とを良好に接続するためにNi、Cu、あるい
はAu等の金属によるメツキあるいは有機金属等を用い
た接合補助層1oがビアフィル導体層8c上に形成され
る。最後に、接合補助層10に電気接続するようにして
その接合補助jlloおよびガラス印刷層9上にCu、
Ni。
A glass printing layer 9 is formed on the uppermost aluminum printing layer 7c. Further, in order to properly connect the uppermost via fill conductor layer 8c and the thick film conductor 11, a bonding auxiliary layer 1o made of plating with a metal such as Ni, Cu, or Au, or an organic metal, etc. is provided on the via fill conductor layer 8c. is formed. Finally, Cu, Cu,
Ni.

Ag、Au等の材質より威る厚膜導体を形成して、本実
施例のセラミック積層基板が構成される。そして、この
ように構成されるセラミック積層基板の厚膜導体11上
には各種チップ素子等が形成されることになる。
The ceramic laminated substrate of this embodiment is constructed by forming a thick film conductor that is more effective than materials such as Ag and Au. Various chip elements and the like are then formed on the thick film conductor 11 of the ceramic laminated substrate constructed in this way.

次に、第2図のフローチャートを用いて本実施例のセラ
ミック積層基板の製造工程をより詳しく説明する。まず
、アルミナチーブlとなるアルミナグリーンシートテー
プを用意して(ステップA)このテープにパンチングを
行い、スルーホール2を形成する(ステップB)。そし
て、そのスルーホール2内に高融点金属導体層を圧入あ
るいは印刷によって充填する(ステップC)、そして、
テープ上に内層導体3となる高融点金属導体をスクリー
ン印刷法により印刷しくステップD)、引き続き100
〜150℃の温度にてその導体を乾燥させる(ステップ
E)。そして、この導体およびテープ上にアルξす印刷
層4aとなるアルミナペーストを印刷しくステップF)
、引き続きそのアル主ナベ−ストを乾燥させる(ステッ
プG)、さらに、そのペーストの開口部にビアフィル導
体層5aとなるビアフィル導体を印刷しくステップH)
、引き続きその導体を乾燥させる(ステップ■)。
Next, the manufacturing process of the ceramic multilayer substrate of this example will be explained in more detail using the flowchart of FIG. First, an alumina green sheet tape to be used as alumina cheese 1 is prepared (step A), and the tape is punched to form through holes 2 (step B). Then, the through hole 2 is filled with a high melting point metal conductor layer by press-fitting or printing (step C), and
Step D): Print a high-melting point metal conductor that will become the inner layer conductor 3 on the tape using a screen printing method, followed by step 100.
Dry the conductor at a temperature of ˜150° C. (Step E). Then, print alumina paste, which will become the printing layer 4a, on this conductor and tape (step F).
Then, the aluminum paste is dried (Step G), and a via fill conductor, which will become the via fill conductor layer 5a, is printed in the opening of the paste (Step H).
, and then continue to dry the conductor (step ■).

その後、ステップF〜ステップIまでの工程は必要な厚
さを得るために繰り返し実施され(本実施例では1回繰
り返す)アルミナ印刷1i14bおよびビアフィル導体
層5bとなるアルミナペーストおよびビアフィル導体が
形成される。そして、この上からさらにアルミナ印刷層
4cとなるアルミナペーストを印刷しくステップJ)、
引き続きそのアルミナペーストを乾燥させる(ステップ
K)。
Thereafter, the steps from Step F to Step I are repeated to obtain the required thickness (in this example, it is repeated once) to form the alumina paste and via fill conductor that will become the alumina printing 1i14b and the via fill conductor layer 5b. . Then, on top of this, alumina paste is further printed to form the alumina printing layer 4c (step J).
The alumina paste is then dried (step K).

以上のスチップD〜ステップKまでの一連の工程により
、−要分の配線が形成される。そして、必要に応じてこ
れらの工程を繰り返すことにより、テープ上に多層の配
線が形成される。尚、本実施例においてはステップD〜
ステップにの工程を1回繰り返して実施しており、それ
らの工程により内層導体6、アルミナ印刷層7a、ビア
フィル導体層8a、アル主す印刷層7b、ビアフィル導
体Ji8bおよびアルミナ印刷層7Cとなる導体および
アルミナペーストを形成している。
Through the series of steps from chip D to step K described above, -required wiring is formed. Then, by repeating these steps as necessary, multilayer wiring is formed on the tape. Note that in this embodiment, steps D~
The process in step 1 is repeated once, and the conductor becomes the inner layer conductor 6, alumina print layer 7a, via fill conductor layer 8a, aluminum main print layer 7b, via fill conductor Ji8b and alumina print layer 7C. and forming an alumina paste.

その後、同様にしてビアフィル導体層8cとなる高融点
金属導体を印刷しくステップL)、引き続きこの導体を
乾燥させる(ステップM)、そうした上で、この状態の
基板を約350 ’Cの温度にて16時間仮焼を行った
後(ステップN)、1600°Cの温度、Nz十Hz 
+HzOの雰囲気中にて24時間、同時に焼成を行う(
ステップ○)。尚、内層導体3.6およびビアフィル導
体層5a、5b、8a、8b、8cの材質として用いら
れる高融点金属導体の融点はアルξすの焼成可能な最低
温度より高い温度であることが要求される。
Thereafter, a high melting point metal conductor that will become the via fill conductor layer 8c is printed in the same manner (step L), and this conductor is subsequently dried (step M). After that, the substrate in this state is heated to a temperature of about 350'C. After 16 hours of calcination (step N), temperature of 1600°C, Nz 10Hz
Simultaneously firing for 24 hours in +HzO atmosphere (
Step ○). Note that the melting point of the high melting point metal conductor used as the material for the inner layer conductor 3.6 and the via fill conductor layers 5a, 5b, 8a, 8b, and 8c is required to be higher than the lowest temperature at which aluminum can be fired. Ru.

次に、アルミナ印刷NIc上に表出したビアフィル導体
層8c上を除いてアルミナ印刷層7C上の全面にガラス
印刷層9となる厚膜ガラス層を印刷しくステップP)、
そのガラス層を125〜150″Cの温度にて乾燥しく
ステップQ)、引き続き850〜900°Cの温度、大
気あるいはN2雰囲気中にて1時間、焼成を行う(ステ
ップR)。
Next, a thick film glass layer that will become the glass printing layer 9 is printed on the entire surface of the alumina printing layer 7C except for the via fill conductor layer 8c exposed on the alumina printing NIC (Step P),
The glass layer is dried at a temperature of 125-150"C (step Q), and then fired for 1 hour at a temperature of 850-900"C in air or N2 atmosphere (step R).

尚、この時用いられるガラス層の材質としては、−船釣
に厚膜層間ガラスとして用いられているガラスを用いる
ことができ、有機溶剤にガラスの成分、ガラス結晶核と
なる酸化物、およびセラミック等のフィラー等を分散し
たペーストを印刷すればよいものである。又、必要に応
じてステップPおよびQを繰り返すことにより、多層の
ガラス印刷層9を形成することができる。
The material of the glass layer to be used at this time is: - Glass used as thick film interlayer glass for boat fishing can be used, and an organic solvent containing glass components, oxides serving as glass crystal nuclei, and ceramics can be used. It is sufficient to print a paste in which a filler such as the like is dispersed. Moreover, by repeating steps P and Q as necessary, a multilayer glass printing layer 9 can be formed.

次に、Ni、CuあるいはAuはビアフィル導体層8c
上にメツキしくステップS)、このメツキ層をシンタリ
ングする(ステップT)ことにより、接合補助層10を
形成する。尚、ステップTのシンタリング工程は省略し
ても良く、また、この接合補助JiilOはPt等のペ
ーストを印刷し、これを850〜900℃の温度にて焼
成することにより形成しても良い。
Next, Ni, Cu or Au is applied to the via fill conductor layer 8c.
The bonding auxiliary layer 10 is formed by plating the top layer (step S) and sintering this plating layer (step T). Incidentally, the sintering process in Step T may be omitted, and the joining aid JailO may be formed by printing a paste of Pt or the like and firing it at a temperature of 850 to 900°C.

さらに、PからQまでの厚膜ガラス層形成工程および接
合層形成工程S、Tを逆の順に行っても同様の効果が得
られる。又、次工程の厚膜導体焼成(ステップ■)を空
気中で行う場合には、接合層形成を先に行い、かつ接合
層としては下地のW。
Furthermore, the same effect can be obtained even if the thick film glass layer forming steps from P to Q and the bonding layer forming steps S and T are performed in the reverse order. In addition, when the next step of firing the thick film conductor (step ①) is performed in air, the bonding layer is formed first, and the bonding layer is W as the base.

Mo等の酸化されやすい金属より威るビアフィルを酸化
より防止できるような耐酸化層をあわせて形成する必要
がある。
It is also necessary to form an oxidation-resistant layer that can prevent via fill from oxidizing, which is more dangerous than metals that are easily oxidized such as Mo.

次に、接合補助層10およびガラス印刷層9上にCu、
Ni、Ag、Au系の材質より威る厚膜導体を印刷しく
ステップU)、この導体を乾燥し、引き続き850℃の
温度、大気あるいはN!雰囲気中に1時間焼成を行い、
本実施例のセラミック積層基板の製造工程を終える(ス
テップ■)。
Next, Cu,
In order to print a thick film conductor that is more effective than Ni, Ag, or Au based materials (Step U), this conductor is dried and then exposed to a temperature of 850°C, air or N! Baking is performed in the atmosphere for 1 hour,
The manufacturing process of the ceramic multilayer substrate of this example is completed (step ①).

そこで、上述のようにして形成される本実施例によると
、ステップMまでに形成された各層をステップN、Oに
て同時に焼成しており、その後、ガラス印刷層9を焼成
形成している。その結果、ステップN、 0の焼成工程
にてアルミナ印刷層7a、7b、7cにピンホール等の
欠陥が生じたとしても、ガラス印刷層9を形成する際に
ガラス印刷層9がその欠陥内に入り込み、その欠陥を塞
ぐことができ、その欠陥を通して上下導体間での初期的
な、あるいは耐久試験下でのシッートを防止することが
できる。
Therefore, in this embodiment formed as described above, each layer formed up to Step M is fired simultaneously in Steps N and O, and then the glass printing layer 9 is fired. As a result, even if defects such as pinholes occur in the alumina print layers 7a, 7b, and 7c during the firing process in steps N and 0, the glass print layer 9 will not fit into the defects when forming the glass print layer 9. It is possible to fill the defect and prevent initial or durability test seating between the upper and lower conductors through the defect.

第3図はアルaす印刷層7c上に追加形成するガラス印
刷層9の層数と欠陥(ピンホール)深さとの関係を示す
グラフである。尚、測定結果は最悪条件での評価を行う
ために、アルミナ印刷層に予め直径100μmで深さが
20amの欠陥(ピンホール)を形成しておき、この上
にガラス印刷層9を印刷して焼成した後の値である。又
、第3図中丸プロットはガラス膜厚を20μmにした時
の値であり、三角プロットはガラス膜厚を10μmにし
た時の値である。第3図からガラス印刷層9を形成する
ことによる効果が顕著であることが確認でき、また、そ
の層数を増すことにより、より効果があることがわかる
。特に、ガラス膜厚を20μmとし、ガラス印刷層9を
2層形成する場合には直径100μmという大きなピン
ホールにもかかわらず、はぼ完全に穴を塞ぐことができ
る。
FIG. 3 is a graph showing the relationship between the number of glass printing layers 9 additionally formed on the aluminum printing layer 7c and the defect (pinhole) depth. In order to evaluate the measurement results under the worst conditions, a defect (pinhole) with a diameter of 100 μm and a depth of 20 am was formed in advance on the alumina printing layer, and a glass printing layer 9 was printed on top of this. This is the value after firing. Moreover, the circle plot in FIG. 3 is the value when the glass film thickness is 20 μm, and the triangular plot is the value when the glass film thickness is 10 μm. From FIG. 3, it can be confirmed that the effect of forming the glass printing layer 9 is significant, and it can also be seen that increasing the number of layers produces a greater effect. In particular, when the glass film thickness is 20 μm and two glass printing layers 9 are formed, even a pinhole as large as 100 μm in diameter can be almost completely filled.

第4図は絶縁破壊電圧と度数(個数)との関係を示すグ
ラフであり、そのうち同図(a)にガラス印刷層9を形
成しない時の結果を、同図(ロ)に膜厚17μmのガラ
ス印刷層9を形成した時の結果を示す。尚、図中7は絶
縁破壊電圧の平均値を示している。第4図(a)および
(ロ)を比較すればわかるように、ガラス印刷層9を形
成した場合には、比較的高い絶縁破壊電圧にて破壊に至
るセラミック積層基板が増加しており、絶縁信頼性が向
上していることがわかる。
Fig. 4 is a graph showing the relationship between dielectric breakdown voltage and frequency (number of pieces), of which Fig. 4(a) shows the results when the glass printing layer 9 is not formed, and Fig. 4(b) shows the results when the glass printing layer 9 is not formed. The results when glass printing layer 9 was formed are shown. Note that 7 in the figure indicates the average value of the dielectric breakdown voltage. As can be seen by comparing FIGS. 4(a) and (b), when the glass printed layer 9 is formed, the number of ceramic multilayer substrates that break down at a relatively high dielectric breakdown voltage increases, and It can be seen that reliability has improved.

以上、本発明を上述の実施例を用いて説明したが、本発
明はそれに限定されることなく、その主旨を逸脱しない
限り例えば以下に示す如く種々変形可能である。
Although the present invention has been described above using the above-mentioned embodiments, the present invention is not limited thereto and can be modified in various ways, for example as shown below, without departing from the spirit thereof.

■上記実施例のセラミック積層基板の製造方法は、印刷
積層法を採用しているが、レイヤー積層法により製造し
ても良い、この場合には、複数のアルミナグリーンシー
トをラミネートし焼成した後に、その上にガラス印刷層
を形成すれば良い。
■The method for manufacturing the ceramic laminated substrate in the above example employs the printing lamination method, but it may also be manufactured by the layer lamination method. In this case, after laminating and firing a plurality of alumina green sheets, A glass printing layer may be formed thereon.

尚、レイヤー積層法の製造工程上の理由から、および印
刷積層法にて形成されるセラミック積層基板の1層分の
アルミナ層の厚さ(60μm程度)に対して、レイヤー
積層法にて形成されるセラミック積層基板のアルよす層
の厚さ(200〜250μm程度)が十分に厚いという
理由から、レイヤー積層法においては異物が混入する可
能性が比較的低く、又、仮にピンホールが生じたとして
もそれがアルミナ層の表面にまで達する可能性が小さい
ものであり、従って、本発明による効果は印刷積層法を
採用した場合の方が顕著である。又、言うまでもなくセ
ラミック積層基板の製造方法は印刷積層法とレイヤー積
層法を複合したものであっても良い。
In addition, for reasons related to the manufacturing process of the layer lamination method, and for the thickness of one layer of alumina layer (approximately 60 μm) of the ceramic laminated substrate formed by the printing lamination method, the thickness of the alumina layer formed by the layer lamination method is Because the aluminum layer of the ceramic laminated substrate is sufficiently thick (approximately 200 to 250 μm), there is a relatively low possibility that foreign matter will be mixed in with the layer lamination method, and even if pinholes occur, Even so, there is a small possibility that it will reach the surface of the alumina layer, and therefore, the effects of the present invention are more remarkable when the printing lamination method is adopted. Needless to say, the method for manufacturing the ceramic laminate substrate may be a combination of the printing lamination method and the layer lamination method.

■本発明で言うセラミック層としては、上記実施例にて
用いたアルξすの他に窒化アルa (/IN) 、ム’
14 トC3A1zOs  ’ 2S i Ox)等の
セラ壽ツクが使用可能である。さらに、セラミック層に
ガラスおよびセラミックスより成る複合材料を用い、内
層導体材料としてAg、Cu、Ni■上記実施例ではガ
ラス印刷層9を第2図のステップP−Rに示す印刷→乾
燥→焼成の工程にょり形成しているが、そのガラス層は
ペースト状のものを印刷するのではなく、フィルム状の
ものを全54フ9層の表面上に配置し、このフィルム状
のものを焼成することにより形成しても良い。又、本発
明で言う絶縁層としては、ガラス以外にも例えばセラミ
ックとガラスの複合物質等の絶縁材料が採用できるが、
第2図に示したように、ステップOにてアルミナ層等を
同時焼成した後に形成し、焼成されるものであるために
、その絶縁材料の焼成時にアルミナ層等が極力再焼成さ
れないようにするのが望ましく、従って、その絶縁材料
はセラ信頼性を向上できるという効果がある。
■The ceramic layer used in the present invention may include aluminum nitride a (/IN), mu'
14, C3A1zOs'2S i Ox), etc. can be used. Furthermore, a composite material consisting of glass and ceramics is used for the ceramic layer, and the inner layer conductor material is Ag, Cu, Ni. The glass layer is formed by a process, but instead of printing a paste-like glass layer, a film-like layer is placed on the surface of the 9 layers of 54 sheets in total, and this film-like layer is fired. It may be formed by. Furthermore, as the insulating layer referred to in the present invention, insulating materials other than glass, such as a composite material of ceramic and glass, can be used.
As shown in Figure 2, since it is formed and fired after co-firing the alumina layer etc. in step O, it is necessary to prevent the alumina layer etc. from being re-baked as much as possible when firing the insulating material. Therefore, the insulating material has the effect of improving the reliability of the cell.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のセラ逅ツク積層基板の断面
図、第2図は一実施例の製造工程を示すフローチャート
、第3図はガラス印刷層と欠陥深さとの関係を示すグラ
フ、第4図(a)、 (b)は絶縁破壊電圧と度数との
関係を示すグラフである。 1・・・アルミナテープ、3.6・・・内層導体、4a
。 4b、4c、7a、7b、7cmアルξす印刷層。 5a、5b、8a、8b、8cm・・ビアフィル導体層
、9・・・ガラス印刷層、11・・・厚膜導体。 ンホールを効果的に塞ぐために、印刷時あるいは焼成時
の粘度が小さいもの(例えば20万CPS以下)を使用
するのが望ましい。
Fig. 1 is a cross-sectional view of a ceramic laminated board according to an embodiment of the present invention, Fig. 2 is a flowchart showing the manufacturing process of the embodiment, and Fig. 3 is a graph showing the relationship between the glass printing layer and defect depth. , FIGS. 4(a) and 4(b) are graphs showing the relationship between dielectric breakdown voltage and frequency. 1... Alumina tape, 3.6... Inner layer conductor, 4a
. 4b, 4c, 7a, 7b, 7cm aluminum printing layer. 5a, 5b, 8a, 8b, 8cm... Via fill conductor layer, 9... Glass printing layer, 11... Thick film conductor. In order to effectively close the holes, it is desirable to use a material that has a low viscosity during printing or firing (for example, 200,000 CPS or less).

Claims (2)

【特許請求の範囲】[Claims] (1) セラミック層と該セラミック層の焼成可能な最
低温度より高い融点を有する高融点金属導体層とが交互
に積層形成され、かつ、前記高融点金属導体層に電気接
続して導体層を形成してなるセラミック積層基板におい
て、 前記セラミック層の焼成可能な最低温度より低温度にて
焼成可能な絶縁層を前記セラミック層の表面上に形成し
たことを特徴とするセラミック積層基板。
(1) A ceramic layer and a high melting point metal conductor layer having a melting point higher than the lowest firing temperature of the ceramic layer are alternately laminated and are electrically connected to the high melting point metal conductor layer to form a conductor layer. What is claimed is: 1. A ceramic multilayer board comprising: an insulating layer sinterable at a temperature lower than the minimum temperature at which the ceramic layer can be sintered; an insulating layer formed on the surface of the ceramic layer.
(2) セラミック層と該セラミック層の焼成温度より
高い融点を有する高融点金属導体層とを交互に積層形成
し、これを同時に所定の焼成温度にて焼成する工程と、 前記セラミック層の表面上に絶縁層を形成し、この絶縁
層を前記焼成温度より低温度にて焼成する工程と、 前記絶縁層の上に、前記高融点金属導体層に電気接続す
るように導体層を形成する工程と を備えることを特徴とするセラミック積層基板およびそ
の製造方法。
(2) Alternately laminating ceramic layers and refractory metal conductor layers having a melting point higher than the firing temperature of the ceramic layers, and firing them at a predetermined firing temperature at the same time; forming an insulating layer on the insulating layer and firing the insulating layer at a temperature lower than the firing temperature; and forming a conductive layer on the insulating layer so as to be electrically connected to the high melting point metal conductor layer. A ceramic laminate substrate and a method for manufacturing the same, characterized by comprising:
JP1203642A 1989-08-05 1989-08-05 Method for manufacturing ceramic laminated substrate Expired - Fee Related JPH0828577B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP1203642A JPH0828577B2 (en) 1989-08-05 1989-08-05 Method for manufacturing ceramic laminated substrate
DE4024612A DE4024612C2 (en) 1989-08-05 1990-08-02 Ceramic, multi-layered substrate and manufacturing process
US08/007,020 US5290375A (en) 1989-08-05 1993-01-21 Process for manufacturing ceramic multilayer substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1203642A JPH0828577B2 (en) 1989-08-05 1989-08-05 Method for manufacturing ceramic laminated substrate

Publications (2)

Publication Number Publication Date
JPH0368195A true JPH0368195A (en) 1991-03-25
JPH0828577B2 JPH0828577B2 (en) 1996-03-21

Family

ID=16477426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1203642A Expired - Fee Related JPH0828577B2 (en) 1989-08-05 1989-08-05 Method for manufacturing ceramic laminated substrate

Country Status (2)

Country Link
JP (1) JPH0828577B2 (en)
DE (1) DE4024612C2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
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JPH0529765A (en) * 1990-08-23 1993-02-05 Ngk Insulators Ltd Ceramic multilayer wiring board and manufacture thereof
WO2012067253A1 (en) * 2010-11-17 2012-05-24 パナソニック株式会社 Ceramic substrate and method for producing same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3666321B2 (en) * 1999-10-21 2005-06-29 株式会社村田製作所 Multilayer ceramic substrate and manufacturing method thereof

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JPS6049670U (en) * 1983-09-12 1985-04-08 株式会社日立製作所 Wet multilayer board
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JPS62296599A (en) * 1986-06-17 1987-12-23 日立化成工業株式会社 Composite ceramic multilayer interconnection board and manufacture of the same
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JPS5586195A (en) * 1978-12-25 1980-06-28 Fujitsu Ltd Method of fabricating multilayer circuit board
JPS6049670U (en) * 1983-09-12 1985-04-08 株式会社日立製作所 Wet multilayer board
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JPH0529765A (en) * 1990-08-23 1993-02-05 Ngk Insulators Ltd Ceramic multilayer wiring board and manufacture thereof
WO2012067253A1 (en) * 2010-11-17 2012-05-24 パナソニック株式会社 Ceramic substrate and method for producing same

Also Published As

Publication number Publication date
JPH0828577B2 (en) 1996-03-21
DE4024612A1 (en) 1991-02-07
DE4024612C2 (en) 2001-06-13

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