JPS62296600A - Composite ceramic multilayer interconnection board and manufacture of the same - Google Patents

Composite ceramic multilayer interconnection board and manufacture of the same

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Publication number
JPS62296600A
JPS62296600A JP14097086A JP14097086A JPS62296600A JP S62296600 A JPS62296600 A JP S62296600A JP 14097086 A JP14097086 A JP 14097086A JP 14097086 A JP14097086 A JP 14097086A JP S62296600 A JPS62296600 A JP S62296600A
Authority
JP
Japan
Prior art keywords
layer
glass
composite ceramic
ceramic multilayer
conductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14097086A
Other languages
Japanese (ja)
Inventor
三森 誠司
上山 守
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP14097086A priority Critical patent/JPS62296600A/en
Publication of JPS62296600A publication Critical patent/JPS62296600A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 3、発明の詳細な説明 (産業上の利用分野) 本発明は混成集積回路などの電子回路部品に用いられる
複合セラミック多層錠υ板およびその製造法に関する。
Detailed Description of the Invention 3. Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a composite ceramic multilayer lock plate used for electronic circuit components such as hybrid integrated circuits, and a method for manufacturing the same.

(従来の技術) セラミック配線板にはグリーン法により製造されるセラ
ミック配線板と厚膜法により製造されるセラミック配線
板とがある。最近のセラミック配線板は、高密度化、高
機能化に伴い、グリーン法によって製造されたセラミッ
ク配線板上に厚膜法によシ導体層、抵抗体層等を形成し
た複合セラミック多層配線板が一部実用化されている。
(Prior Art) Ceramic wiring boards include ceramic wiring boards manufactured by the green method and ceramic wiring boards manufactured by the thick film method. Recent ceramic wiring boards have become more dense and highly functional, and composite ceramic multilayer wiring boards are now being developed, in which conductor layers, resistor layers, etc. are formed using the thick film method on ceramic wiring boards manufactured using the green method. Some of them have been put into practical use.

従来の複合セラミック多層配線板は、第3図に示すよう
にアルミナセラミックス1中にMo、W等の高融点金属
粉を主成分とした内部導体層2を形成し、その内部導体
層2の一部をスルーホール5を介して表面に引出し、ス
ルーホール5上に露出した内部導体層2の露出面にめっ
きなどの方法でN4層8を形成し、さらにその上面にA
uなどの貴金属層6を形成したものが一般に知られてい
る。
As shown in FIG. 3, a conventional composite ceramic multilayer wiring board has an internal conductor layer 2 mainly composed of powder of a high melting point metal such as Mo or W formed in an alumina ceramic 1. N4 layer 8 is formed on the exposed surface of internal conductor layer 2 exposed above through hole 5 by a method such as plating, and A
Those in which a noble metal layer 6 such as U is formed are generally known.

(発明が解決しようとする問題点) 第3図に示す複合セラミック多層配線板を用いて電子回
路部品を製造する場合、上面に高温焼成用のAg/Pd
粉を主成分とした外部導体層、 )1.uOx粉を主成
分とした抵抗体層などの厚膜回路を形成するが、これら
の厚膜回路は通常大気中で焼結されるため内部導体層お
よび内部導体層の露出面に形成する金属層は酸化しない
ようにすることが必要である。しかし々から上記のよう
な構造の複合セラミック配線板を用いて800〜950
℃の温度で焼成すると下地の内部導体層および金属層が
酸化される欠点がある。
(Problems to be Solved by the Invention) When manufacturing electronic circuit components using the composite ceramic multilayer wiring board shown in FIG.
Outer conductor layer mainly composed of powder, )1. Thick film circuits such as resistor layers are formed using uOx powder as a main component, but since these thick film circuits are usually sintered in the atmosphere, the inner conductor layer and the metal layer formed on the exposed surface of the inner conductor layer are It is necessary to prevent it from oxidizing. However, using a composite ceramic wiring board with the above structure,
There is a drawback that firing at a temperature of 30°F (°C) oxidizes the underlying internal conductor layer and metal layer.

この対策として低温焼成(650℃以下)用のAg/P
d粉を主成分とした外部導体層、 It、 u Oa粉
を主成分とした抵抗体層などの厚膜回路を形成したり、
キユアリングタイプの導体層、カーボン系の抵抗体層な
どの厚膜回路を形成してみたが、これらは高温焼成の厚
膜回路に比較し、’1’Cn(抵抗の変動率]が大きく
信頼性に劣るという欠点がある。
As a countermeasure for this, Ag/P for low temperature firing (below 650℃)
Forming thick film circuits such as an external conductor layer mainly composed of d powder and a resistor layer mainly composed of It, u Oa powder,
I tried forming thick film circuits such as a curing type conductor layer and a carbon-based resistor layer, but compared to thick film circuits fired at high temperatures, these had a large '1' Cn (resistance variation rate) and were more reliable. It has the disadvantage of being inferior in gender.

(問題点を解決するだめの手段) 本発明は上記のような欠点のない複合セラミック多層配
線板およびその製造法を提供することを目的とするもの
である。
(Means for Solving the Problems) An object of the present invention is to provide a composite ceramic multilayer wiring board and a method for manufacturing the same, which are free from the above-mentioned drawbacks.

本発明者らは上記の欠点について種々検討した結果、グ
リーン法によシ一部を表面に露出させてアルミナセラミ
ックス中にMo、W等の高融点金属粉を主成分とした内
部導体層を形成し、ついでスルーホールを介して表面に
露出した内部導体層上の表面のほぼ中央部を残しアルミ
ナセラミックスの表面にかけてガラスペーストを塗布し
、中性雰囲気中で焼成してバイアホールを有するガラス
層を形成したところ800〜950℃の温度で焼成して
も下地の内部導体層およびNi層、Ag/Pd層が酸化
しないことを確認した。
As a result of various studies on the above-mentioned drawbacks, the present inventors formed an internal conductor layer mainly composed of high melting point metal powder such as Mo and W in alumina ceramics by exposing a part of the material to the surface using the green method. Then, glass paste is applied to the surface of the alumina ceramics, leaving approximately the center of the surface on the internal conductor layer exposed to the surface through the through hole, and fired in a neutral atmosphere to form a glass layer with via holes. When formed, it was confirmed that the underlying internal conductor layer, Ni layer, and Ag/Pd layer were not oxidized even when fired at a temperature of 800 to 950°C.

本発明は一部を表面に露出させてアルミナセラミックス
中に内蔵された内部導体層、前記内部導体層の露出面に
形成されたNi層、Ni層上に形成されたAg/Pd層
およびアルミナセラミックスの表面とAg /Pd層上
にバイアホールを設けて形成されたガラス層からなる複
合セラミック多層配線板並びにグリーン法により一部を
表面に露出させてアルミナセラミックス中に内部導体層
を形成し。
The present invention provides an internal conductor layer built into alumina ceramics with a part exposed on the surface, a Ni layer formed on the exposed surface of the internal conductor layer, an Ag/Pd layer formed on the Ni layer, and alumina ceramics. A composite ceramic multilayer wiring board consisting of a glass layer formed by providing via holes on the surface of the substrate and the Ag/Pd layer, and an internal conductor layer formed in the alumina ceramics by exposing a portion to the surface using the green method.

ついで内部導体層の露出面にNi層を形成し、さらにN
i層上にAg/Pd層を形成し、しかる後Ag/Pd層
の表面のほぼ中央部を残しアルミナセラミックスの表面
にかけてガラスペーストを塗布し、中性雰囲気中で焼成
してバイアホールを有するガラス層を形成する複合セラ
ミック多層配線板の製造法に関する。
Next, a Ni layer is formed on the exposed surface of the internal conductor layer, and then a Ni layer is formed on the exposed surface of the internal conductor layer.
An Ag/Pd layer is formed on the i-layer, and then a glass paste is applied to the surface of the alumina ceramics, leaving approximately the center of the surface of the Ag/Pd layer, and is fired in a neutral atmosphere to form glass with via holes. The present invention relates to a method for manufacturing a composite ceramic multilayer wiring board in which layers are formed.

本発明において内部導体層を形成する材料としては、 
Mo 、 Mo / Mn、 W等の高融点金属が用い
られる。
In the present invention, the materials forming the inner conductor layer include:
High melting point metals such as Mo, Mo/Mn, and W are used.

Ni層の形成は、めっき、蒸着、Niペーストを塗布し
、焼付けて形成するなどの方法があり特に制限はないが
9本発明では、無電%Ni/Pめつき。
The Ni layer can be formed by plating, vapor deposition, applying Ni paste, and baking, and is not particularly limited.9 In the present invention, electroless Ni/P plating is used.

無電解Ni/Bめつき、電解めっき等のめつき法でNi
層を形成することが好ましい。このときのめつきの厚さ
は、内部導体層の露出面の表面粗さにより異なるが、0
.5〜8μmの厚さであることが好ましく、1μm以上
の厚さであればNi層にピンホ面 一部がなく、特性1作業性の点でさらに好ましい。
Ni by plating methods such as electroless Ni/B plating and electrolytic plating.
Preferably, a layer is formed. The thickness of the plating at this time varies depending on the surface roughness of the exposed surface of the internal conductor layer, but
.. A thickness of 5 to 8 μm is preferable, and a thickness of 1 μm or more is more preferable from the point of view of characteristic 1 workability since the Ni layer does not have a portion of the pinhole surface.

Ag/Pd層の形成は、転写により形成する方法。The Ag/Pd layer is formed by transfer.

Ag /Pdペーストを塗布し、熱処理により焼付けて
形成する方法などがあり特に制限はないが9本発明では
Ag/Pdペーストを塗布し、それを還元又は中性雰囲
気中で熱処理し、Ag/Pdペーストを焼付けて形成す
ることが好ましい。
There is a method of applying Ag/Pd paste and baking it by heat treatment, but there is no particular limitation. Preferably, the paste is formed by baking.

Ag/Pd層の厚さについては特に制限はないが。There is no particular restriction on the thickness of the Ag/Pd layer.

3〜20μmの厚さであればAg/Pd層にピンホール
がなく1作業性の面で好ましい。
A thickness of 3 to 20 μm is preferable in terms of ease of workability since there are no pinholes in the Ag/Pd layer.

ガラス層の形成に用いられるガラスは、非晶質ガラス、
結晶化ガラスで中性雰囲気中において焼結可能なガラス
が用いられる。なお軟化点が650℃〜Ni層の融点以
下のガラスを用いれば、厚膜回路形成時にガラスがアル
ミナセラミックスに拡散しないので好ましい。まだ高融
点金属より酸化物の生成自由エネルギーの高いガラスを
用いれば。
The glass used to form the glass layer is amorphous glass,
A crystallized glass that can be sintered in a neutral atmosphere is used. It is preferable to use glass having a softening point of 650° C. to the melting point of the Ni layer, since the glass will not diffuse into the alumina ceramics when forming a thick film circuit. If you use glass, which still has a higher free energy of oxide formation than high-melting point metals.

ガラスが高融点金属に拡散しても高融点金属が酸化しな
いので好ましい。
This is preferable because the high melting point metal does not oxidize even if the glass diffuses into the high melting point metal.

ガラスペーストを焼付けるには、 N2. Ar等の中
性雰囲気中で焼成しなければならず、酸化性雰囲気中で
焼成するとNi層、内部導体層等が酸化L 1寸た還元
性雰囲気中で焼成するとガラスペースト中の有機バイン
ダーが残存してガラスの焼結を妨げるという欠点が生じ
る。
To bake the glass paste, use N2. Firing must be done in a neutral atmosphere such as Ar; firing in an oxidizing atmosphere will cause the Ni layer, internal conductor layer, etc. to oxidize. If firing in a reducing atmosphere, the organic binder in the glass paste will remain. This results in the disadvantage that the sintering of the glass is hindered.

本発明になる複合セラミック多層配線板は、必要ニ応じ
バイアホールおよびバイアホールの周辺のガラス層上に
ガラスを含有したAg/Pd、 Ag/Pt、 Pt、
 Au 等を主成分とした外部導体層。
The composite ceramic multilayer wiring board according to the present invention includes glass-containing Ag/Pd, Ag/Pt, Pt, glass-containing glass on the via hole and the glass layer around the via hole as necessary.
An outer conductor layer mainly composed of Au or the like.

Ru Osを主成分とした抵抗体層などの厚膜回路を形
成してもよい。
A thick film circuit such as a resistor layer mainly composed of RuOs may be formed.

(実施例) 以下実施例により本発明を説明する。(Example) The present invention will be explained below with reference to Examples.

実施例1 厚さ0.8 mmのアルミナセラミックグリーンシート
(アルミナ純度96重i1′%)(以下グリーンシート
という)を2枚50 X 50 mmの寸法に切断し。
Example 1 Two alumina ceramic green sheets (alumina purity 96w/i1'%) (hereinafter referred to as green sheets) with a thickness of 0.8 mm were cut into a size of 50 x 50 mm.

このうちの1枚に1G径0.6 mmの穴(スルーホー
ル)を形成し9次いでスルーホール内にWペースト(旭
化学社製、商品名3TW−1200)を充填すると共に
片側の表面に前述と同じWペーストを印刷し、そして乾
燥後他の1枚のグリーンシートの上に前記グリーンシー
トの表面にWペーストを印刷した面を下にして重ね、そ
れを100℃、6kg/c−の条件で加熱加圧し、その
後弱還元性(H2)雰囲気中で1600℃の温度で1時
間保持してグリーンシートを焼結させると共にWペース
トを焼結させ第2図に示すように一部を表面に露出させ
てアルミナセラミックス1中に内部導体層2を形成した
セラミック配線板を得た。
A hole (through hole) with a 1G diameter of 0.6 mm was formed in one of these sheets, and W paste (manufactured by Asahi Chemical Co., Ltd., trade name 3TW-1200) was then filled in the through hole, and the surface of one side was filled with the After drying, the same W paste was printed, and after drying, the green sheet was placed on top of another green sheet with the side with the W paste printed facing down, and then heated at 100°C and 6 kg/c-. After that, the green sheet was sintered by heating and pressurizing at 1,600°C for 1 hour in a weakly reducing (H2) atmosphere, and the W paste was sintered, with a part of the material being exposed to the surface as shown in Figure 2. A ceramic wiring board was obtained in which an internal conductor layer 2 was formed in an exposed alumina ceramic 1.

次に上記内部導体層2の露出面を活性化液(日本カニゼ
ン社製の陽3活性液)で活性化し9次いで無電解Ni/
Pめつき(日本カニゼン製、商品名f9−680)を行
ない、水洗、乾燥して第1図に示すように厚さ4μmの
Niめっき層3を形成した。
Next, the exposed surface of the internal conductor layer 2 was activated with an activating solution (Yo3 activating solution manufactured by Nippon Kanigen Co., Ltd.).
P plating (manufactured by Nippon Kanigen, trade name f9-680) was performed, washed with water, and dried to form a Ni plating layer 3 with a thickness of 4 μm as shown in FIG.

ついでNiめつき層3の上面の中央部に、平均粒径が0
.3μmのAg粉80重量%とPd粉20重量%とを混
合し、この混合物100重量部に対し、アクリル系バイ
ンダー(デュポン社製、商品名φ5200)2重量部お
よび有機溶剤としてブチルカルピトールアセテートを1
0重量部添加し、3本ロールにて混練して得たAg /
 Pdペーストを直径が0.4 vtse 熱処理後の
厚さが10μmの厚さになるように印刷し、乾燥後還元
雰囲気中で750℃の温度で10分間熱処理してAg 
/ Pd層9を形成した。
Next, in the center of the upper surface of the Ni plating layer 3, an average grain size of 0
.. 80% by weight of 3 μm Ag powder and 20% by weight of Pd powder were mixed, and to 100 parts by weight of this mixture, 2 parts by weight of an acrylic binder (trade name: φ5200, manufactured by DuPont) and butyl carpitol acetate were added as an organic solvent. 1
Ag obtained by adding 0 parts by weight and kneading with three rolls /
Pd paste was printed to have a diameter of 0.4 vtse and a thickness of 10 μm after heat treatment, and after drying, it was heat treated at a temperature of 750 °C for 10 minutes in a reducing atmosphere to form Ag.
/ Pd layer 9 was formed.

この後810m 50重量%、 BaO24重ii s
、 Altos6重量%およびCa020重量%よりな
る軟化点が860℃のガラスを平均粒径3μmに粉砕し
、との粉砕したガラス粉末100重量部に対し、アクリ
ル系バインダー(デュポン社製、商品名す5200)2
重量部および有機溶剤としてブチルカルピトールアセテ
ートを10重量部添加し、3本ロールにて混練してペー
スト化した。次に前記のガラスペーストを、Ag/Pd
層9上の中央部を直径0.2 an口残し、アルミナセ
ラミックス1の表面にかけて幅が0.4 mのリング状
に、そして乾燥後の厚さが40μmの厚さになるように
印刷し、乾燥後N2雰囲気中で900℃の温度で20分
間熱処理してガラス層4およびバイアホール7を形成し
た複合セラミック多層配線板を得た。なお第1図および
第2図において5はスルーホールである。
After this 810m 50wt%, BaO24w ii s
A glass with a softening point of 860°C consisting of 6% by weight of Altos and 20% by weight of Ca0 was ground to an average particle size of 3 μm, and 100 parts by weight of the ground glass powder was mixed with an acrylic binder (manufactured by DuPont, trade name 5200). )2
10 parts by weight of butylcarpitol acetate as an organic solvent were added, and the mixture was kneaded with three rolls to form a paste. Next, the glass paste was mixed with Ag/Pd
A hole of 0.2 mm in diameter was left in the center of the layer 9, and printed on the surface of the alumina ceramics 1 in a ring shape with a width of 0.4 m and a thickness of 40 μm after drying. After drying, heat treatment was performed at a temperature of 900° C. for 20 minutes in an N2 atmosphere to obtain a composite ceramic multilayer wiring board in which a glass layer 4 and via holes 7 were formed. Note that in FIGS. 1 and 2, 5 is a through hole.

実施例2 実施例1で得たセラミック配線板の内部露出面に実施例
1と同じ活性化液を用いて活性化し1次  ′いで無電
解Nl/Bめつき(日本カニゼン社製、商品名8B−5
5)を行ない、水洗、乾燥して厚さ5μmのNiめっき
層を形成し、さらにNiめつき層の上面の中央部に実施
例1と同様のAg/Pdペーストを用いて実施例1と同
様の方法で厚さ10μmのAg / Pd層を形成した
。この後5iOz54重量%。
Example 2 The internal exposed surface of the ceramic wiring board obtained in Example 1 was activated using the same activation solution as in Example 1, and subjected to primary electroless Nl/B plating (manufactured by Nippon Kanigen Co., Ltd., product name 8B). -5
5), washed with water and dried to form a Ni plating layer with a thickness of 5 μm, and then the same Ag/Pd paste as in Example 1 was used in the center of the upper surface of the Ni plating layer. An Ag/Pd layer with a thickness of 10 μm was formed using the method described above. After this, 5iOz 54% by weight.

Al!os 13重量%、 Zn07重1:%、Ca0
25重−i%およびMg01重量%よりなる軟化点が8
20℃のガラスを平均粒径3μmに粉砕し、この粉砕し
たガラス粉末100重量部に対し、アクリル系バインダ
ー(デュポン社製、商品名す5200)2重量部および
有機溶剤としてブチルカルピトーlO− ルアセテートを10重量部添加し、3本ロールにて混練
してペースト化した。次に前記のガラスペーストを実施
例1と同様の方法で、Ag/Pd層上の中央部を直径0
.2 m残し、アルミナセラミックスの表面にかけて幅
が0.4 mmのリング状に、そして乾燥後の厚さが5
0μmの厚さになるように印刷し、乾燥後N3雰囲気中
で850℃の温度で10分間熱処理してガラス層および
バイアホールを形成した複合セラミック多層配線板を得
た。
Al! os 13% by weight, Zn07 weight 1:%, Ca0
Softening point of 25 wt-i% and Mg01 wt% is 8
Glass at 20°C was ground to an average particle size of 3 μm, and 2 parts by weight of an acrylic binder (manufactured by DuPont, trade name: 5200) and butylcarpitol lO-1 were added as an organic solvent to 100 parts by weight of the ground glass powder. 10 parts by weight of acetate was added and kneaded using three rolls to form a paste. Next, the above glass paste was applied to the central part on the Ag/Pd layer in the same manner as in Example 1 to a diameter of 0.
.. Leave 2 m, and form a ring shape with a width of 0.4 mm over the surface of the alumina ceramic, and a thickness of 5 mm after drying.
A composite ceramic multilayer wiring board was obtained by printing to a thickness of 0 μm, drying, and heat-treating at 850° C. for 10 minutes in an N3 atmosphere to form a glass layer and via holes.

実施例3 実施例1で得たセラミック配線板の内部露出面に実施例
2と同じめっき液を用いて実施例1と同様の方法で厚さ
3μmのN1めつき層を形成し、さらにNiめっき層の
上面の中央部に実施例1と同様のAg/Pdペーストを
用いて実施例1と同様の方法で12μmの厚さにAg 
/ Pd層を形成した。この後Cu系の多層用ガラスペ
ースト(日量フェロ電子社製、商品名1005RCu)
を実施例1と同様の方法で、かつ実施例1と同形状に、
そして乾燥後の厚さが30μmの厚さになるように印刷
し。
Example 3 An N1 plating layer with a thickness of 3 μm was formed on the internal exposed surface of the ceramic wiring board obtained in Example 1 using the same plating solution as in Example 2 and in the same manner as in Example 1, and further Ni plating was applied. Ag was applied to the center of the upper surface of the layer to a thickness of 12 μm in the same manner as in Example 1 using the same Ag/Pd paste as in Example 1.
/ A Pd layer was formed. After this, Cu-based multilayer glass paste (manufactured by Nichiryo Ferro Denshi Co., Ltd., trade name 1005RCu)
in the same manner as in Example 1 and in the same shape as in Example 1,
Then, it was printed to a thickness of 30 μm after drying.

乾燥後N2W囲気中で850℃の温度で1時間熱処理し
てガラス層およびバイアホールを形成した複合セラミッ
ク多層配線板を得た。
After drying, it was heat-treated in a N2W atmosphere at a temperature of 850° C. for 1 hour to obtain a composite ceramic multilayer wiring board in which a glass layer and via holes were formed.

比較例1 実施例1で得たセラミック配線板の内部導体層の露出面
に実施例1と同様の方法および実施例1と同様のめつき
液を用いて厚さ4μmのNiめつき層を形成し、さらに
その上面に無電解Auめっき(日本エンゲルハルト社製
、商品名ATOMBX−PC)を行ない、水洗、乾燥し
て厚さ1μmのAuめつき層を形成した複合セラミック
多層配線板を得た。
Comparative Example 1 A Ni plating layer with a thickness of 4 μm was formed on the exposed surface of the internal conductor layer of the ceramic wiring board obtained in Example 1 using the same method as in Example 1 and using the same plating solution as in Example 1. Further, electroless Au plating (manufactured by Nippon Engelhard Co., Ltd., trade name ATOMBX-PC) was performed on the top surface, washed with water, and dried to form a 1 μm thick Au plating layer to obtain a composite ceramic multilayer wiring board. .

次に各実施例で得た複合セラミック多層配線板のバイア
ホール内とバイアホール周辺のガラス層上および比較例
1で得た複合セラミック多層配線板のAuめつき層上に
高温焼成型のガラス含有Ag / Pdペースト(日中
マツセイ社製、商品名≠4846)を印刷し、乾燥後大
気中で850℃の温度で10分間熱処理してガラス含有
Ag / Pdペーストを焼付け、ガラス含有Ag /
 Pd層を形成した。次いでこのガラス含有Ag1Pd
層と内部導体層との接続抵抗および内部導体層の酸化の
有無について観察した。その結果各実施例で得た複合セ
ラミック多層配線板は、接続抵抗は1mΩ以下で変動率
が小さく、内部導体層の酸化は見られなかった。これに
対し比較例1で得た複合セラミック多層配線板は、電気
的導通が得られず、内部導体層が酸化していた。またガ
ラス含有Ag / Pd層の代わシにガラス含有Pt層
、ガラス含有Au層、ガラス含有Ag/Pi層を形成し
ても同様の効果が得られた。
Next, high temperature sintered glass was added to the inside of the via hole and on the glass layer around the via hole of the composite ceramic multilayer wiring board obtained in each example, and on the Au plating layer of the composite ceramic multilayer wiring board obtained in Comparative Example 1. Ag/Pd paste (manufactured by Nichika Matsusei Co., Ltd., trade name≠4846) was printed, and after drying, the glass-containing Ag/Pd paste was baked by heat treatment at a temperature of 850 °C for 10 minutes in the air, and the glass-containing Ag/Pd paste was printed.
A Pd layer was formed. Then this glass-containing Ag1Pd
The connection resistance between the layer and the internal conductor layer and the presence or absence of oxidation of the internal conductor layer were observed. As a result, the composite ceramic multilayer wiring boards obtained in each example had a connection resistance of 1 mΩ or less with a small fluctuation rate, and no oxidation of the internal conductor layer was observed. On the other hand, in the composite ceramic multilayer wiring board obtained in Comparative Example 1, electrical continuity could not be obtained, and the internal conductor layer was oxidized. Similar effects were also obtained by forming a glass-containing Pt layer, a glass-containing Au layer, or a glass-containing Ag/Pi layer instead of the glass-containing Ag/Pd layer.

(発明の効果] 本発明になる複合セラミック多層配線板は、内部導体層
が酸化せず、電気的特性上信頼が高く。
(Effects of the Invention) In the composite ceramic multilayer wiring board according to the present invention, the internal conductor layer does not oxidize and has high reliability in terms of electrical characteristics.

工業的に極めて好適である。It is extremely suitable industrially.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例になる複合セラミック多層配線
板の断面側面図、第2図は本発明の実施例になる複合セ
ラミック多層配線板に用いられるセラミック配線板の断
面側面図および第3図は従来の複合セラミック多層配線
板の断面側面図である。 符号の説明 1・・・アルミナセラミックス 2・・・内部導体層3
・・・N1めつき層      4・・・ガラス層5・
・・スルーホール     6・・・貴金属層7・・・
バイアホール     8・・・Ni19・・・Ag 
/ Pd層 ZI 図 ! 第 2[2] 光3 口 に了ルミナヤラStり、シζ5 9:A>/r〆珊
FIG. 1 is a cross-sectional side view of a composite ceramic multilayer wiring board according to an embodiment of the present invention, FIG. 2 is a cross-sectional side view of a ceramic wiring board used in a composite ceramic multilayer wiring board according to an embodiment of the present invention, and FIG. The figure is a cross-sectional side view of a conventional composite ceramic multilayer wiring board. Explanation of symbols 1...Alumina ceramics 2...Inner conductor layer 3
...N1 plating layer 4...Glass layer 5.
...Through hole 6...Precious metal layer 7...
Via hole 8...Ni19...Ag
/ Pd layer ZI diagram! 2nd [2] Light 3 Lumina Yara St in the mouth, ζ5 9:A>/r〆san

Claims (1)

【特許請求の範囲】 1、一部を表面に露出させてアルミナセラミックス中に
内蔵された内部導体層、前記内部導体層の露出面に形成
されたNi層、Ni層上に形成されたAg/Pd層およ
びアルミナセラミックスの表面とAg/Pd層上にバイ
アホールを設けて形成されたガラス層からなる複合セラ
ミック多層配線板。 2、グリーン法により一部を表面に露出させてアルミナ
セラミックス中に内部導体層を形成し、ついで内部導体
層の露出面にNi層を形成し、さらにNi層上にAg/
Pd層を形成し、しかる後Ag/Pd層の表面のほぼ中
央部を残しアルミナセラミックスの表面にかけてガラス
ペーストを塗布し、中性雰囲気中で焼成してバイアホー
ルを有するガラス層を形成することを特徴とする複合セ
ラミック多層配線板の製造法。
[Claims] 1. An internal conductor layer built into alumina ceramics with a part exposed on the surface, a Ni layer formed on the exposed surface of the internal conductor layer, and an Ag/A layer formed on the Ni layer. A composite ceramic multilayer wiring board consisting of a Pd layer and a glass layer formed by providing via holes on the surface of an alumina ceramic and an Ag/Pd layer. 2. Form an internal conductor layer in alumina ceramics by exposing a part to the surface using the green method, then form a Ni layer on the exposed surface of the internal conductor layer, and then form an Ag/conductor layer on the Ni layer.
A Pd layer is formed, and then a glass paste is applied to the surface of the alumina ceramics, leaving approximately the center of the surface of the Ag/Pd layer, and is fired in a neutral atmosphere to form a glass layer with via holes. A manufacturing method for a characteristic composite ceramic multilayer wiring board.
JP14097086A 1986-06-17 1986-06-17 Composite ceramic multilayer interconnection board and manufacture of the same Pending JPS62296600A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14097086A JPS62296600A (en) 1986-06-17 1986-06-17 Composite ceramic multilayer interconnection board and manufacture of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14097086A JPS62296600A (en) 1986-06-17 1986-06-17 Composite ceramic multilayer interconnection board and manufacture of the same

Publications (1)

Publication Number Publication Date
JPS62296600A true JPS62296600A (en) 1987-12-23

Family

ID=15281067

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14097086A Pending JPS62296600A (en) 1986-06-17 1986-06-17 Composite ceramic multilayer interconnection board and manufacture of the same

Country Status (1)

Country Link
JP (1) JPS62296600A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0368195A (en) * 1989-08-05 1991-03-25 Nippondenso Co Ltd Laminated ceramic board and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0368195A (en) * 1989-08-05 1991-03-25 Nippondenso Co Ltd Laminated ceramic board and manufacture thereof

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