JPH0359516A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To eliminate the need of an outside electric element by arranging 1st and 2nd conductive films and a capacitor at specified positions. CONSTITUTION:The capacitor is arranged at the part of a dead space DS shown by crosshatching. A 1st electrode constituting the capacitor consists of a Cr film g1 for forming a gate electrode, a Cr film d1 for forming a drain electrode, an A1 film d2 for forming a drain electrode and an ITO film ITO1 for a transparent picture element electrode which are formed on a lower transparent glass substrate SUB 1 and a 2nd electrode consists of a light shielding film BM and an ITO film ITO2 for a common transparent picture element electrode which are formed on an upper transparent glass substrate SUB 2. Thus, the outside electric element is made needless.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a liquid crystal display device, and particularly to an active matrix type liquid crystal display device using thin film transistors and the like. [Prior Art] An active matrix type liquid crystal display device is one in which a nonlinear element (switching element) is provided corresponding to each of a plurality of pixel electrodes arranged in a matrix. Theoretically, the liquid crystal in each pixel is always in motion (duty ratio 1.0), so the active method has better contrast than the so-called simple matrix method, which uses a time-division drive method, and is particularly useful for color It is becoming an indispensable technology. A typical switching element is a thin film transistor (TPT). Active matrix liquid crystal display devices using TPT are described in, for example, "12.5-inch active matrix color liquid crystal display with redundant configuration," Nikkei Electronics, pp. 193-210, 1986.
It is known for being published by Nikkei McGraw-Hill on February 15th. In addition, in Japanese Patent Application Laid-open No. 63-115193, a display electrode and a counter electrode provided on the surfaces of a pair of substrates disposed opposite each other are provided at a predetermined portion of each pixel facing each other, and It has been proposed to provide a spacer made of a dielectric material with a large value so that one end is in contact with a display electrode and the other end is in contact with a counter electrode, and to use the spacer as a capacitor for adding an auxiliary capacitance to the cell capacitance. [Problems to be Solved by the Invention] However, in the invention described in Japanese Patent Laid-Open No. 63-115193, it is difficult to provide the spacer for each pixel, and it is also difficult to make the capacitance values the same. An object of the present invention is to eliminate the need for external electrical elements by forming capacitors and resistors using films and materials (liquid crystals) that make up liquid crystal display devices that use thin film transistors and color filters. An object of the present invention is to provide a liquid crystal display device at low cost. Another object of the present invention is to provide a liquid crystal display device that can prevent the occurrence of stray capacitance due to external wiring and fix the ground to form a noise filter, thereby preventing malfunctions of an open RC. be. Still another object of the present invention is to reduce the number of external ICs by forming the above-mentioned capacitors and resistors on a glass substrate to form a flip-flop circuit and an interface circuit, thereby providing a liquid crystal display device at low cost. It's about doing. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Means for Solving the Problems] In order to solve the above problems, the liquid crystal display device of the present invention includes conductive films formed on opposing surfaces of a first substrate and a second substrate, A capacitor is formed by the liquid crystal (used as a dielectric) sealed between both substrates. Further, a resistor is formed by a conductive film (including a semiconductor film) formed on one surface of the first substrate and the second substrate facing each other. These C and R components (in some cases, the L component) are used to form a noise filter that prevents noise from entering the scanning signal line and video signal line, and to take measures against noise in ICs connected in cascade. It also forms emitter follower interface circuits and C and R components of flip-flops. [Operation] Since a noise filter can be formed using C and R, noise can be removed. Since liquid crystal is used as a dielectric, once it is destroyed (short circuited) like a solid capacitor, it will not become unusable and will recover naturally. [Example] Hereinafter, the structure of the present invention will be described together with an example in which the present invention is applied to an active matrix type color liquid crystal display device. Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted. FIG. 2A is a plan view showing one pixel and its surroundings of an active matrix color liquid crystal display device to which the present invention is applied, and FIG. 2B is a cross section taken along the line 11B-nB in FIG. 2A and the display panel. FIG. 2C is a cross-sectional view of the vicinity of the seal portion, and FIG. 2C is a cross-sectional view taken along the line ■C--C of FIG. 2A. Moreover, FIG. 3 (main part plan view) shows a plan view when a plurality of pixels shown in FIG. 2A are arranged. (Pixel Arrangement) As shown in Figure 2A, each pixel is connected to two adjacent scanning signal lines (gate signal line or horizontal signal line) GL and two adjacent video signal lines (drain signal line or vertical signal line). Signal line)
Within the intersection area with DL (within the area surrounded by four signal lines)
Each of the six pixels arranged in is a thin film transistor TPT,
Includes pixel electrode IT○ and additional capacitance Cadd. The scanning signals iGL extend in the column direction, and a plurality of scanning signals iGL are arranged in the row direction. The video signal lines DL extend in the row direction, and a plurality of video signal lines DL are arranged in the column direction. (Overall panel cross-sectional structure) As shown in FIG. 2B, a thin film transistor TPT and a transparent pixel electrode IT○1 are formed on the lower transparent glass substrate 5UBI side with respect to the liquid crystal NLC, and the upper transparent glass substrate 5
On the UBZ side, a color filter FIL and a light-shielding black matrix pattern BM are formed. The lower transparent glass substrate 5UBl side has a thickness of about 1.1 mm, for example. The central part of Figure 2B shows a cross section of one pixel,
The left side shows a cross section of the left edge portion of the transparent glass substrates 5UBI and 5UB2 where external lead wiring is present. The right side shows a cross section of the right edge portion of the transparent glass substrates 5UBI and 5UB2 where no external lead wiring is present. The sealing material SL shown on the left and right sides of FIG. 2B is configured to seal the liquid crystal LC, and the liquid crystal sealing opening (
Transparent glass substrates 5UBI and 5 excluding (not shown)
It is formed along the entire edge Ml of UB2. The sealing material SL is made of, for example, epoxy resin. The common transparent pixel electrode ITO2 on the side of the upper transparent glass substrate 5UBZ is at least at one location. The lower transparent glass substrate 5U is made of silver paste material SIL.
It is connected to the external lead wiring formed on the BI side. This external lead wiring is formed in the same manufacturing process as each of the gate electrode GT, source electrode SDI, and drain electrode SD2 described above. Orientation films 0RII and ○RI2. Transparent pixel electrode work T○, common transparent pixel electrode ITO1 protective film PSVI and PSV2,
Each layer of the insulating film GI is formed inside the sealing material SL. The polarizing plate POL has a lower transparent glass substrate 5UBI,
It is formed on each outer surface of the upper transparent glass substrate 5UB2. The liquid crystal LC has a lower alignment film 0R that sets the direction of the liquid crystal molecules.
II and the upper alignment film 0RI2, and sealed by a sealing portion SL. The lower alignment film 0RII is formed on the protective film PSV4 on the lower transparent glass base @5UBI side. On the inner surface (liquid crystal side) of the upper transparent glass substrate 5UB2, a light shielding film BM, a color filter FIL, and a protective film PSV are provided.
2. A common transparent pixel electrode (COM) IrO2 and an upper alignment film RI2 are sequentially laminated. This liquid crystal display device has a lower transparent glass substrate 5UB1 side,
Each layer on the upper transparent glass substrate 5UBZ side is formed separately, and then the upper and lower transparent glass substrates 5UBI and 5UB2 are formed.
It is assembled by overlapping the two and sealing the liquid crystal LC between them. (Thin film transistor TPT> The thin film transistor TPT operates in such a way that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and drain becomes small, and when the bias is reduced to zero, the channel resistance becomes large.Thin film transistor of each pixel TPT is 3 within a pixel.
It is divided into two (plurality) of thin film transistors (divided thin film transistors) TFT1, TFT2, and TFT3. Each of the thin film transistors TPTI to TFT3 has substantially the same size (channel length and width are the same). Each of the divided thin film transistors TPTI to TFT3 mainly includes a gate electrode GT, a gate insulating film Gr, i
It is composed of an amorphous Si semiconductor layer AS (intrinsic, not doped with conductivity type determining impurities), a pair of source electrode SD1 and drain electrode SD2. Note that the source and drain are originally determined by the bias polarity between them, and in the circuit of this display device, the polarity is reversed during operation, so it should be understood that the source and drain are interchanged during operation. However, in the following explanation as well, for convenience, one side is fixed as a source and the other side is fixed as a drain. (Gate electrode GT> As shown in detail in FIG. 4 (a plan view depicting only the layers gl, g2, and AS in FIG. 2A), the gate electrode GT is connected in the vertical direction (FIGS. 2A and 2A) from the scanning signal mGL. The gate electrode GT is configured to protrude upward (upward in FIG. 4) (branched into a T-shape).The gate electrode GT is configured to protrude to the formation region of each of the thin film transistors TPTI to TFT3.Thin film transistor TPTI~TF
The respective gate electrodes GT of T3 are integrally formed (as a common gate electrode) and are formed continuously to the scanning signal line GL. The gate electrode GT is formed of a single-layer first conductive film g1 so as not to form a large step in the formation region of the thin film transistor TPT. The first conductive film g1 is formed using, for example, a chromium (Cr) film formed by sputtering, and has a thickness of about 1000 [in]. As shown in FIGS. 2A, 2B, and 4, this gate electrode GT is formed larger than the semiconductor layer AS so as to completely cover it (as viewed from below). Therefore, when a backlight BL such as a fluorescent lamp is attached below the substrate 5UBI, the opaque Cr gate electrode GT casts a shadow, and the backlight light does not shine on the semiconductor layer AS.
A conductive phenomenon, that is, deterioration of the off-characteristics of TPT due to light irradiation becomes less likely to occur. Note that the original size of the gate electrode GT is the minimum width required to span between the source/drain electrode SDI and Sn2 (including the alignment margin between the gate electrode and the source/drain electrode), and the channel width. W
The depth is determined by the ratio to the distance (channel length) L between the source and drain electrodes, that is, the factor W/L that determines the mutual conductance gm. The size of the gate electrode in this embodiment is of course larger than the original size mentioned above. Considering only the function of the gate and light shielding of the gate electrode GT, the gate electrode and its wiring GL may be integrally formed in a single layer, and in this case, Si is used as the opaque conductive material.
A containing Pd], pure A1, and A1 containing Pd
etc. can be selected. (Scanning Signal Line GL> The scanning signal line GL is composed of a composite film consisting of a first conductive film g1 and a second conductive film g2 provided on top of the first conductive film g1. g1 is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is configured integrally with the first conductive film g1.The second conductive film g2 is made of, for example, an aluminum (AQ) film formed by sputtering. , 2000 to 4000 [A,]. The second conductive film g2 reduces the resistance value of the scanning signal gGL and increases the signal transmission speed (improves the writing characteristics of pixel information). In addition, the scanning signal 1iGL is configured such that the width of the second conductive film g2 is smaller than the width of the first conductive film g1.In other words, the scanning signal line GL The step shape of the side wall is gentle. (Gate II! I edge film GI) The insulating film GI is used as a gate insulating film of each of the thin film transistors TPTI to TFT3. The insulating film GI is a gate electrode. The insulating film GI is formed on the upper layer of the GT and the scanning signal line GL.The insulating film GI is formed using, for example, a silicon nitride film formed by plasma CVD, and has a film thickness of about 3000 mm (semiconductor, l1AS). As shown in FIG. 4, the i-type semiconductor layer AS is used as a channel formation region for each of thin film transistors TPTI to TFT3 divided into a plurality of parts.The i-type semiconductor layer AS is made of an amorphous silicon film or polycrystalline silicon. The i-type semiconductor layer AS is formed with a film thickness of approximately 1,800 μm thick.This i-type semiconductor layer AS is made of Si
, are formed successively to the formation of the N4 gate insulating film GI without being exposed to the outside. In addition, P-doped N''1dO (Figure 2B) for ohmic contact is similarly continuously formed to a thickness of approximately 400[lambda].Then, the lower substrate 5UBI is taken out from the CVD apparatus. Then, by photo processing technology, the N+ layer do and i ff1j A S
are patterned into independent islands as shown in FIGS. 2A, 2B, and 4. The i-type semiconductor layer AS is located at the intersection of the scanning signal line OL and the video signal line DL (as shown in detail in FIGS. 2A and 4).
The cross-over section) is also provided between the two. This intersection i-type semiconductor IAs is connected to the scanning signal line G at the intersection.
It is configured to reduce short circuits between L and the video signal line DL. (Source/drain electrodes SDI, Sn2>The source electrodes SDI and drain electrodes SD2 of the thin film transistors TPT1 to TFT3 divided into multiple parts are shown in FIGS. 2A, 2B, and 5 (layers d1 to d1 in FIG. 2A). As shown in detail in the plan view (plan view depicting only d3), they are provided separately on the semiconductor layer AS.
From the lower layer side in contact with the type semiconductor layer dO, the first conductive film d1
, a second conductive film d2, and a third conductive film d3 are sequentially stacked on top of each other. the first conductive film d1 of the source electrode SDI;
The second conductive film d2 and the third conductive film d3 are the drain electrode S
They are formed in the same manufacturing process as each of D2. The first conductive film d1 is a chromium film formed by sputtering, and has a film thickness of 500~]OOOO[A] (in this example, 6
The film thickness is approximately 0.00 [person]. When forming a chromium film thicker, the stress increases, so 2000
[The film should be formed within a range that does not exceed the thickness of a human body. The chromium film has good contact with the N+ type semiconductor layer do. The chromium film constitutes a so-called barrier layer that prevents aluminum of the second conductive film d2, which will be described later, from diffusing into the N+ type semiconductor layer do. The first conductive film d1 includes, in addition to a chromium film, a high melting point metal (Mo, Ti, Ta, W) film, a high melting point metal silicide (M. The N+ layer do is removed using the same photo processing mask or using the first conductive film di as a mask. That is, i, fil A
The portions of the N+ layer do remaining on S except for the first conductive film d1 are removed by self-alignment. At this time, since the N+ layer do is etched so that its entire thickness is removed, the i/i AS is also slightly etched on its surface, but the extent can be controlled by the etching time. Thereafter, the second conductive film d2 is formed by aluminum sputtering to a thickness of 3000 to 4000 [in this embodiment, approximately 3000]. The aluminum film has less stress than the chromium film, can be formed thicker, and is configured to reduce the resistance values of the source electrode SDI, drain electrode SD2, and video signal line DL. In addition to the aluminum film, the second conductive film d2 may be formed of an aluminum film containing silicon (Si) or copper (Cu) as an additive. After patterning the second conductive film d2 using a photoprocessing technique, a third conductive film d3 is formed. This third conductive film d3 is a transparent conductive film (Induim-T) formed by sputtering.
in-Oxide I T○: Nesa membrane),
Film thickness of 00 to 2000 [people] (in this example, 120
It is formed with a film thickness of about 0 [large]. This third conductive film d
3 constitutes a source electrode SDI, a drain electrode SD2, and a video signal iDL, and also constitutes a transparent pixel electrode ITOI. First conductive film d1 of source electrode SDI. drain electrode SD
Each of the first conductive films di of No. 2 extends more inward (into the channel region) than the upper second conductive film d2 and the third conductive film d3. In other words, the first conductive film d1 in these parts is the layer d
2. The configuration is such that the gate length of the thin film transistor TPT can be defined independently of d3. As described above, the source electrode SDI is connected to the transparent pixel electrode IT.
Connected to OI. The source electrode SD1 has a stepped shape of the i-type semiconductor layer AS (the thickness of the first conductive film g1, the thickness of the N+ layer d
It is configured along a step corresponding to the sum of the film thickness of O and the film thickness of the i-type semiconductor layer AS. Specifically, the source electrode SDI includes a first conductive film d1 formed along the step shape of the i-type semiconductor layer AS, and a first conductive film d1 formed along the step shape of the i-type semiconductor layer AS.
(On the upper part of The source electrode SDI is composed of a conductive film d3 and a conductive film d3.
The second conductive film d2 cannot be formed thickly because the chromium film of the first conductive film d1 increases stress and cannot overcome the step shape of the i-type semiconductor layer AS.
It is designed to overcome. In other words, the step coverage is improved by forming the second conductive film d2 thickly. Since the second conductive film d2 can be formed thickly,
This greatly contributes to reducing the resistance value of the source electrode SDI (the same applies to the drain electrode SD2 and the video signal line DL). Since the third conductive film d3 cannot overcome the step shape caused by the i-type semiconductor layer AS of the second conductive film d2, by reducing the size of the second conductive film d2, the exposed first conductive film di configured to connect. The first conductive film d1 and the third conductive film d3 not only have good adhesion but also have a small step shape at the connection between them.
Can be connected reliably. (Pixel Electrode IT○1) The transparent pixel electrode IT○1 is provided for each pixel, and constitutes one of the pixel electrodes of the liquid crystal display section. The transparent pixel electrode IT○1 is divided into three transparent pixel electrodes (divided transparent pixel electrodes) El, E2, and E3 corresponding to each of the thin film transistors TFTI-TFT3 divided into a plurality of pixels. The transparent pixel electrodes El-E3 are each connected to the source electrode SD of the thin film transistor TPT. Each of the transparent pixel electrodes El-E3 is patterned to have substantially the same area. In this way, by dividing the thin film transistor TPT of one pixel into a plurality of medium thin film transistors TPT1 to TPT3, and connecting each of the plurality of divided transparent pixel electrodes E1 to E3 to each of the plurality of divided thin film transistors TPTI to TFT3. , a divided portion (e.g. TF
Even if TI) becomes a point defect, it is no longer a point defect when looking at the entire pixel (TFT2 and TFT3 are not defective), so
The probability of point defects can be reduced, and defects can be made difficult to see. Further, by configuring each of the divided transparent pixel electrodes El to E3 of the pixel to have substantially the same area, each liquid crystal composed of each of the transparent pixel electrodes E1 to E3 and the common transparent pixel electrode ITO2 The capacitance (Cpix) can be made uniform. (Protective film PSVI> A protective film PSVI is provided over the thin film transistor TPT and the transparent pixel electrode IrO1. The protective film PSV1 is mainly formed to protect the thin film transistor TPT from moisture etc. The protective film PSVI is made of, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD, and has a high resistance to moisture.
Formed with a film thickness of approximately (Light-shielding film BM3) A shielding film BM is provided on the upper substrate 5UBZ side to prevent external light (light from above in FIG. 2B) from entering the i-type semiconductor layer AS used as a channel formation region, The pattern is as shown by the hatching in FIG. In addition, FIG. 6 shows the ITO film layer d3 in FIG. 2A,
FIG. 3 is a plan view depicting only the filter IFIL and the light shielding film BM. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film that has a high light-shielding property, and in this embodiment, the chromium film is formed by sputtering to a thickness of about 1300 [A]. Therefore, the common semiconductor layer AS of TPTI~3 is sandwiched between the upper and lower light shielding films BM and the thick gate electrode GT, and that portion is not exposed to external natural light or backlight light. The light shielding film BM is formed in a shape (black matrix) as shown by the hunting part in FIG. 6, and the effective display area of one pixel is partitioned by this grid. Therefore, the outline of each pixel becomes clear due to the light shielding film BM, and the contrast is improved. In other words, the light shielding film BM has two functions: shielding the semiconductor layer AS from light and serving as a black matrix. In addition, the backlight is installed on the 5UBZ side, and the 5UBI
can also be set as the observation side (externally exposed side). (Common electrode IT○2) The common transparent pixel electrode ITO2 is connected to the lower transparent glass substrate 5U.
Opposing the transparent pixel electrode ITOI provided for each pixel on the BI side, the optical state of the liquid crystal changes in response to the potential difference (electric field) between each pixel electrode ITOI and the common electrode IrO2. This common transparent pixel electrode ITO2 has a common voltage Vco
m is applied. Common voltage Vc
om is an intermediate potential between the low-level opening voltage Vdm1n and the high-level opening voltage Vdmax applied to the video signal MDL. (Color filter FIL> The color filter FIL is constructed by coloring a dyed base material made of a resin material such as acrylic resin with a dye. (Figure 7) is formed in a dot shape (Figure 7) and is colored differently (Figure 7 depicts only the third conductive film layer d3 and color filter J'1FIL in Figure 3, R, G, H). Each filter is 45''' 135° and has a cross hatch).The color filter FIL is formed thick so as to cover all of the pixel electrodes ITOI (El to E3) as shown in Figure 6. The light shielding film BM is formed inside the periphery of the pixel electrode ITOI so as to overlap with the color filter FIL and the edge portion of the pixel electrode ITO1.The color filter FIL can be formed as follows.First, A dyed base material is formed on the surface of the upper transparent glass substrate 5UB2, and the dyed base material other than the red filter forming area is removed using photolithography technology.After this, the dyed base material is dyed with a red dye and subjected to a fixing treatment, A red filter R is formed.Next, by performing similar steps, a green filter G and a blue filter B are sequentially formed.The protective film PSV2 is formed by dyeing the color filter FIL in different colors to the liquid crystal LC. The protective film PSV2 is provided to prevent leakage. The protective film PSV2 is made of a transparent resin material such as acrylic resin or epoxy resin. (Pixel Arrangement) Each pixel of the liquid crystal display section has a third As shown in FIG. 7 and FIG. 7, a plurality of pixel lines are arranged in the same column direction as the direction in which the scanning signal line OL extends, and constitute pixel columns Xi, X2, X3, X4, etc., respectively. Pixel rows X1, X2.X3.X4
．． Each pixel of... is a thin film transistor TFTI~
The TFT 3 and the transparent pixel electrodes E1 to E3 are arranged in the same position. That is, odd numbered pixel columns Xi, X3 .・・・
・Each pixel is a thin film transistor TPT1 to TFT.
The transparent pixel electrodes E1 to E3 are arranged on the left side, and the transparent pixel electrodes E1 to E3 are arranged on the right side. Odd pixel columns Xi, X3.・・・
.g4 pixel columns adjacent to each other in the row direction X2. X4.・
The pixels of each of the odd-numbered pixel columns Xi, X3 . . . . each pixel is made up of pixels that are symmetrically turned upside down with respect to the extending direction of the video signal line DL. That is, pixel row X2. X4. In each pixel, the thin film transistors TPTI to TFT3 are arranged on the right side, and the transparent pixel electrodes El-E3 are arranged on the left side. Then, pixel row X2. X4. Each pixel of...
The pixels of each of the pixel columns X 1 , X 3 , . . . are moved (shifted) by half a pixel interval in the column direction. In other words, the interval between each pixel in the pixel row X is set to 1.0 (1,
0 pitch), the next pixel column X has a pixel interval of 1°O, and is shifted by 0.5 pixel interval (0.5 pitch) from the previous pixel column X in the column direction. The video signal line DL extending in the row direction between each pixel is configured to extend in the column direction by a half pixel interval (0.5 pitch) between each pixel column X. As a result, as shown in FIG. 7, the pixel on which the predetermined color filter is formed in the previous pixel row The pixels on which color filters are formed (for example, the pixels on which red filter R is formed in pixel row X4) are separated by 1.5 pixel intervals (1.5 pitches), and RG
The color filter FIL of B has a triangular arrangement. The RGB triangular arrangement structure of the color filter FIL can improve the mixing of each color, and therefore can improve the resolution of a color image. Moreover, since the video signal line DL extends in the column direction by only half a pixel interval between each pixel column X, it does not intersect with the adjacent video signal line DL. Therefore, video signal line D
It is possible to eliminate the routing of L and reduce its occupied area, and it is also possible to eliminate the detour of the video signal line DL and eliminate the multilayer wiring structure. (Whole Display Panel Equivalent Circuit) FIG. 8 shows an equal-sized circuit of this liquid crystal display device. XiG, Xi+IG, . . . are video signal lines DL connected to pixels in which the green filter G is formed. XiB, Xi+IB, . . . are video signal lines DL connected to pixels on which the blue filter B is applied. X i + I R, X i + 2 R, ... are,
This is a video signal fiDL connected to a pixel in which a red filter R is formed. These video signal lines DL are selected by a video signal activation circuit. Yi is a scanning signal line GL that selects the pixel column X1 shown in FIGS. 3 and 7. Similarly, Yi+1. Yi+2. Each of the pixel rows X2 . X3. . . . is a scanning signal line GL that selects each of the following. These scanning signal lines GL are connected to a vertical scanning circuit. (Structure of additional capacitance Cadd) Each of the transparent pixel electrodes E1 to E3 is a thin film transistor T.
It is bent into an L-shape so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to PT. As is clear from FIG. 2C, in this superposition, each of the transparent pixel electrodes E to E3 is connected to one electrode PL.
2, and a storage capacitor element (electrostatic capacitor element) Cadd is configured in which the adjacent scanning signal line GL is the other electrode PLI. The dielectric film of this storage capacitor element Cadd is an insulating film G used as a gate insulating film of a thin film transistor TFT.
It is composed of the same layer as I. As is clear from FIG. 4, the storage capacitor Cadd is formed in the widened portion of the first layer g1 of the gate Al0L. Note that the layer g1 in the portion intersecting with the drain line DL
is made thin to reduce the probability of short circuit with the drain line. A portion between each of the transparent pixel electrodes E1 to E3 and the capacitor electrode line (gl), which are overlapped to form the storage capacitor element Cadd, is provided with a layer that can be used to overcome a one-step difference shape, similar to the source electrode SDI. In order to prevent the transparent pixel electrode ITOI from disconnecting, an island region made up of the first conductive film d1 and the second conductive film d2 is provided. This island region is configured to be as small as possible so as not to reduce the area (aperture ratio) of the transparent pixel electrode IT○1. (Equivalent circuit of additional capacitance Cadd and its operation) The equivalent circuit of the pixel shown in FIG. 2A is shown in FIG. 9. In FIG. 9, Cgs is the gate electrode GT of the thin film transistor TPT.
and a parasitic capacitance formed between the source electrode SDI. The dielectric film of parasitic capacitance jtcgs is an insulating film GI. Cp
ix is a liquid crystal capacitance formed between the transparent pixel electrode ITOI (PIX) and the common transparent pixel electrode ITO2 (COM). The dielectric film of the liquid crystal capacitor Cpix is the liquid crystal LC1 protective film p.
sv1 and alignment films 0RII and 0RI2. , vlc
is the midpoint potential. The storage capacitor element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vic when the TFT switches. Expressing this situation using the formula, ΔV lc= ((Cgs/ (Cgs+Cadd+C
pix)) XΔVg. Here, ΔVlc is ΔVg
represents the change in midpoint potential due to This change ΔVIC
causes a DC component applied to the liquid crystal, but the retention capacity Ca
The larger dd is, the smaller its value can be. In addition, the holding capacitor Cadd also has the effect of lengthening the discharge time, so that video information is stored for a long time after the TPT is turned off. Reduction of DC component applied to liquid crystal LC. It is possible to improve the lifespan of the liquid crystal LC and reduce image retention where the previous image remains when switching the liquid crystal display screen. As mentioned above, since the gate electrode GT is made large enough to completely cover the semiconductor layer AS, the overlapping area with the source/drain electrodes SDI and SD2 increases, and therefore the parasitic capacitance Cgs increases and the midpoint potential VLC is the gate (
This has the opposite effect of becoming more susceptible to the influence of the scanning signal Vg. However, by providing the holding capacitor Cadd, this disadvantage can also be eliminated. The storage capacitance of the storage capacitor element Cadd is 4 to 8 times the liquid crystal capacitance Cpix (4・Cp
ix<Cadd<1lcpix), superposition capacitance Cgs
8 to 32 times (8・Cgs<Cadd<32・C
gs). (Connection method of additional capacitance Cadd electrode line) As shown in FIG. ) Connect to IrO2. As shown in FIG. 2B, the common transparent pixel electrode ITO2 is connected to an external wiring at the peripheral edge of the liquid crystal display device by means of a silver paste material SL. Furthermore, some of the conductive layers (gl and g2) of this external lead wiring are formed in the same manufacturing process as the scanning signal line GL. As a result, the final stage capacitor electrode g
GL can be easily connected to the common transparent pixel electrode ITO2. Or, as shown by the dotted line in FIG. 8, the final stage (first stage) capacitor electrode Ii! GL may be connected to the first stage (final stage) scanning signal gGL. Note that this connection can be made by internal wiring within the liquid crystal display section or external wiring. (DC cancellation by additional capacitance Cadd scanning signal) This liquid crystal display device is based on the DC cancellation method (DC cancellation method) described in Japanese Patent Application No. 62-95125 previously filed by the applicant of the present invention. Diagram (time chart)
As shown in FIG. 2, by controlling the drive voltage of the scanning signal line DL, the DC component applied to the liquid crystal LC can be further reduced. In FIG. 10, Vi is the driving voltage of an arbitrary scanning signal AffiGL, and Vi+1 is the driving voltage of the scanning signal line GL at the next stage. Vee is the scanning signal line GL
Low level driving voltage Vdm1n applied to V
d d is a high-level drive voltage V d max applied to the scanning signal line OL. The voltage changes ΔVyu to ΔV4 of the midpoint potential v1c (see FIG. 9) at each time t=ti to t4 are as follows. 1=11:ΔV1=-(CgS/C)・V21=12:
ΔVz=+(Cgs/C)(V1+V2)-(Cadd
/C)・V 2 1=1. :ΔV,=-(Cgs/C)・V1+(Cad
d/C)・(V1+V2) 1=14:Δv4=-(Cadd/C)・Vl,
Total pixel capacity fk: C = Cgs + Cpix + add Here, if the drive voltage applied to the scanning signal line GL is sufficient (see below)

[See Note 1), the DC voltage applied to the liquid crystal LC is ΔV, +ΔV4=(Cadd-V2-Cgs-Vl)/
If Cadd-v2=CgS-vl, then the DC voltage applied to the liquid crystal LC becomes O. [Note] At times t1 and t2, the change in scanning iVi affects the midpoint potential Vlc, but during the period from t2 to t, the midpoint potential V1c is made the same potential as the video signal potential through the signal line Xi ( sufficient writing of the video signal). The potential applied to the liquid crystal is almost determined by the potential immediately after the TPT is turned off (the TPT off period is overwhelmingly longer than the on period). Therefore, calculation of the DC component applied to the liquid crystal during period t1
~t can be almost ignored, and it is only necessary to consider the potential immediately after the TPT is turned off, that is, the influence during transients at times t3 and t4. Note that the polarity of the video signal Vi is inverted for each frame or line, and the DC component due to the video signal itself is zero. In other words, in the DC cancellation method, the drop caused by the pull in of the midpoint potential vlc by the superimposed capacitor Cgs is boosted by the drive voltage applied to the storage capacitor element Cadd and the next stage scanning signal line GL (capacitive electrode line). The direct current component applied to the liquid crystal LC can be made extremely small. As a result, the life of the liquid crystal LC of the liquid crystal display device can be improved. Of course, if the gate GT is made larger to improve the light shielding effect, the storage capacitance Ca will increase accordingly.
dd The value of d may be increased. (Capacitor, Resistor) FIG. 1A is a sectional view showing a configuration example of a capacitor according to the present invention, and FIG. 1B is a plan view of this capacitor. FIG. 1C is a sectional view showing a configuration example of a resistor according to the present invention. FIG. 1D is an equivalent circuit diagram with C1R added. FIG. 1E is a plan view of an LCD showing locations of capacitors and resistors according to the present invention. First, locations where capacitors and resistors are formed in a liquid crystal display section (liquid crystal display panel LCD) will be explained using FIG. 1E. 5UBI is a lower transparent glass substrate, 5UB2 is an upper transparent glass substrate, DP is a liquid crystal display screen, and DS is a dead space between wirings. A capacitor is formed in a dead space DS shown by a thin line, and a resistor is formed in a dead space DS shown by a diagonal line. Since the capacitor uses liquid crystal as a dielectric, it is formed under the upper transparent glass substrate 5UB2 in a portion where the liquid crystal is present. Next, the capacitor according to the present invention will be explained using FIG. 1A and FIG. 1B. Ten capacitors are placed in the dead space DS shown by the mesh lines in FIG. 1E. The first electrode constituting the capacitor of this example is a Cr film g1 for forming a gate electrode, a Cr film d1 for forming a drain electrode, and an Al film d2 for forming a drain electrode, which are formed on the lower transparent glass substrate 5UBI. , and an IT○ film ITOI for a transparent pixel electrode. Protective film P
SVI may or may not be present. Note that the 5-int film formed on each surface of the transparent glass substrates 5UB1 and 5UB2 is for surface flattening. The second electrode constituting the capacitor includes a light shielding film BM formed on the upper transparent glass substrate 5UB2 and an ITO film rTO2 for a common transparent pixel electrode.
Consists of. Liquid crystal LC is used as the dielectric. In addition, as shown in FIG. 1B, even if there is misalignment between the upper transparent glass substrate and the lower transparent glass substrate, the electrode E of the first step and the second electrode E2 are arranged so that the necessary electrode area can be obtained.
is pulled out almost at right angles. Next, the resistor according to the present invention will be explained using FIG. 1C. Ten resistors are arranged in the dead space DS shown by diagonal lines in FIG. 1E. In this example, the ITO film TOI for the common transparent pixel electrode is used.
is used as a resistance layer. crgg for gate electrode formation
l, Cr film d1 for drain electrode formation, A1 film d2 for drain electrode formation. and TOWAITOI are resistor lead wiring. Next, the equivalent circuit will be explained using FIG. 1D. T
The constants of the element for blunting the waveform between ABl and TaB2 between D and D are C,=C4=220pF, C,=100
PF, R=1, Ω, C□=C2=lμF. Here, in order to form C of 200P F, there is a distance of 5 m between the upper transparent glass substrate 5UB2 and the lower transparent glass substrate 5UB1.
Relative permittivity of LCD using corner electrodes ε, = 6, LCD
Assuming a gap of 6.6 pm (between substrates), it becomes 6x5x5xlO-''. Also, to form a resistance of 1Ω, the specific resistance of the T○ film must be 1000μΩ, and the sheet resistance is 83Ω/
For example, if the width is 1m++, the length is about 12m+. As described above, according to this embodiment, since the external C1R component is not required, the cost per component and processing cost are reduced, and the cost can be reduced. In addition, these C1R components (or L components in some cases) can be used to form noise filters that prevent noise from entering the scanning signal line and video signal line, and to take noise countermeasures for ICs connected in cascade. Alternatively, the C and R components of a flip-flop can be formed. Furthermore, since liquid crystal LC is used as the dielectric of the capacitor, it will not break down (short circuit) like a solid capacitor.
Even if the device is damaged, it will not become unusable and will recover naturally. As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course. For example, the layer structure of the capacitor shown in FIG. 1A and the layer structure of the resistor shown in FIG. 1C are merely examples, and various structures can be adopted. Furthermore, although this embodiment shows an inverted staggered structure in which gate electrode formation → gate insulating film formation → semiconductor layer formation → source/drain electrode formation, the present invention is also effective in a staggered structure in which the vertical relationship or the order of formation is reversed. be. [Effects of the Invention] As explained above, according to the present invention, external C, R
Since components are no longer needed, parts costs and processing costs are lower, reducing costs. Further, since a noise filter can be formed using C1R, noise can be reduced. Furthermore, since liquid crystal is used as the dielectric material of the capacitor, even if it is destroyed (shorted) like a solid capacitor, it will not become unusable and will recover naturally. Furthermore, since the wiring pattern is fixed, it is possible to prevent stray capacitance from occurring due to external wiring.

[Brief explanation of drawings]

FIG. 1A is a cross-sectional view showing an example of the structure of a capacitor according to the present invention, FIG. 1B is a plan view of the capacitor, FIG. 1C is a cross-sectional view showing an example of the structure of a resistor according to the present invention, and FIG. , C, and R are added. FIG. 1E is a plan view of an LCD showing the placement locations of capacitors and resistors according to the present invention. FIG. 2A is an active matrix type that is Embodiment I of the present invention. FIG. 2B is a plan view of a main part showing one pixel of the liquid crystal display section of a color liquid crystal display device; FIG. 2B is a cross-sectional view of the portion taken along the nB-JIB cutting line in FIG. is the 2nd A
A sectional view taken along the nc-nc cutting line in the figure. FIG. 3 is a plan view of a main part of a liquid crystal display section in which a plurality of pixels shown in FIG. 2A are arranged, and FIGS. 4 to 6 are plane views depicting only predetermined layers of pixels shown in FIG. 2A. figure. FIG. 7 is a plan view of the main part in a state in which only the pixel electrode layer and color filter layer shown in FIG. The equivalent circuit diagram, Figure 9, is the second
The equivalent circuit diagram of the pixel shown in FIG. In the figure, SUB...transparent glass substrate, GL...scanning signal line, DL...video signal line, GI...insulating film, GT
...gate electrode, AS...i-type semiconductor layer, SD...
・Source electrode or drain electrode, psv...protective film,
LS...light shielding film, LC...liquid crystal, TPT...thin film transistor, ITO...transparent electrode, g, d...conductive film, Cadd...holding capacitor element, Cgs...superimposed capacitor , Cpix... is the liquid crystal capacitance (numerical subscripts after alphabetic characters are omitted). Figure 1D Figure 1E! m Figure 9 Figure 10 l t2 t5t4

Claims (1)

[Claims] 1. First and second conductive films respectively provided on the opposing surfaces of first and second substrates arranged to face each other, and a liquid crystal sealed between the two substrates. A liquid crystal display device characterized in that a capacitor composed of the following is arranged at a predetermined position. 2. A liquid crystal display device, characterized in that a resistor made of a conductive film provided on one side of opposing first and second substrates is arranged at a predetermined position.