JPH0359528A - Electrostatic breakdown preventing means for liquid crystal display device - Google Patents

Abstract

PURPOSE:To all the prevention of an electrostatic breakdown and all the turn-on inspection to be compatible with each other by allowing a part of wirings for short- circuiting each scanning signal line and a part of wirings for short-circuiting each video signal lien to approach each other at the distance of a minute gap. CONSTITUTION:Each picture element is arranged in an area surrounded by four pieces of signal lines in the intersection area of two pieces of adjacent scanning signal lines (gate signal line or horizontal signal line) GL and two pieces of adjacent video signal lines (drain signal line or vertical signal line)DL. Also, each picture element contains a thin film transistor TFT, a pixel electrode ITO1 and an additional capacity Cadd, the scanning signal line is extended in the row direction, plural pieces are arranged in the line direction, and the video image signal line DL is extended in the line direction, and plural pieces are arranged in the row direction. In this state, an electrostatic breakdown preventing means is constituted by allowing a part of wiring for short- circuiting each scanning signal line GL and a part of wirings for short-circuiting each video signal line DL to approach at the distance of a minute gap. In such a manner, the electrostatic breakdown of a gate insulating film is prevented, and also, the all turn-on inspection can be executed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to electrostatic damage prevention means for liquid crystal display devices, and in particular to electrostatic damage prevention for active matrix type liquid crystal display devices using thin film transistors and the like. Concerning means.

[Conventional technology]

An active matrix type liquid crystal display device is one in which a nonlinear element (switching element) is provided corresponding to each of a plurality of pixel electrodes arranged in a matrix.

Theoretically, the liquid crystal in each pixel is always open (duty ratio 1.0), so the active method has better contrast than the so-called simple matrix method, which uses a time-division drive method, especially in color. It is becoming an indispensable technology. A typical switching element is a thin film transistor (TPT).

A liquid crystal display device in which a TPT and a pixel electrode are constituent elements of a pixel has a liquid crystal display section (liquid crystal display panel) in which a plurality of pixels are arranged in a matrix. Each pixel of the liquid crystal display section is formed by the intersection of two adjacent scanning signal lines (also referred to as gate signal lines or horizontal signal lines) and two adjacent video signal lines (also referred to as drain signal lines or vertical signal lines). located within the area. The scanning signal lines extend in the column direction (horizontal direction) and are arranged in plural in the row direction (vertical direction). On the other hand, the video signal lines extend in the row direction intersecting the scanning signal lines, and are arranged in plural in the column direction.

The liquid crystal display section includes a lower transparent glass substrate on which a thin film transistor, a transparent pixel electrode, a protective film for the thin film transistor, and an alignment film are sequentially provided, a color filter, a protective film for the color filter, a common transparent pixel electrode, and an alignment film are sequentially provided. It is composed of an upper transparent glass substrate, a liquid crystal enclosed and sealed between both plates, and a sealing member for the liquid crystal.

A transparent pixel electrode and a thin film transistor are provided for each pixel. Further, one of the source electrode and the drain electrode of the thin film transistor is connected to a transparent pixel electrode, and the other electrode is connected to a video signal line, and
The gate electrode is connected to a scanning signal line.

The active matrix liquid crystal display device using TPT is described in, for example, "12.5-inch active matrix color liquid crystal display with redundant configuration," Nikkei Electronics, pp. 193-210, 1986.
It is known for being published by Nikkei McGraw-Hill on February 15th.

[Problem to be solved by the invention]

During the manufacturing process, the scanning signal line and video signal line are electrically floating, so if static electricity enters the scanning signal line or video signal line, Gate II! There was a problem in that the i-edge film was destroyed and the scanning signal line and the video signal line were short-circuited. To prevent this, before cutting the lower transparent glass substrate from a large glass plate, wiring for preventing electrostatic damage is provided to short-circuit each scanning signal line and each video signal line. After the wiring formation is completed, the lower transparent glass substrate is separated from the wiring for preventing electrostatic damage by cutting the lower transparent glass substrate. However, if the scanning signal line and video signal line are short-circuited to prevent electrostatic damage, it becomes impossible to perform a full-light inspection to check for liquid crystal irregularities, disconnections, TPT checks, and short-circuits between the gate and drain lines. There's a problem.

An object of the present invention is to provide an electrostatic damage prevention means that can both prevent electrostatic damage and perform an all-lights-on inspection.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, the electrostatic damage prevention means of the present invention is such that a part of the wiring in which each scanning signal line is short-circuited and a part of the wiring in which each video signal line is short-circuited are separated from each other by a minute gap. It is characterized by being close to each other.

Further, the electrostatic damage prevention means of the present invention is characterized in that a part of the wiring in which each scanning signal line is short-circuited and a part of the wiring in which each video signal line is short-circuited are overlapped with each other with an insulating film interposed therebetween. shall be.

[Effect]

A part of the wiring that short-circuited each scanning signal line and a part of the wiring that shorted each video signal line are close to each other with a small gap between them, so when static electricity enters the wiring, the wiring that is close to each other is A discharge occurs, which prevents electrostatic damage to the gate insulating film and also allows for full-light inspection.

In addition, part of the wiring that short-circuited each scanning signal line and a part of the wiring that shorted each video signal line are overlapped with a $@ membrane, and when static electricity enters the wiring, the liquid crystal display By forming the above-mentioned part so that it is destroyed before the gate insulating film used as a part, it is possible to prevent electrostatic damage of the gate insulating film and also to perform a full lighting test.

〔Example〕

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below along with an embodiment in which the present invention is applied to an active matrix color liquid crystal display device.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

FIG. 2A is a plan view showing one pixel and its surroundings of an active matrix color liquid crystal display device to which the present invention is applied, and FIG. 2B is a cross-sectional view taken along the line IIB-IIB of FIG. 2A and the display panel. FIG. 2C is a cross-sectional view of the vicinity of the seal portion, and FIG. 2C is a cross-sectional view taken along the line c-nc in FIG. 2A.

Moreover, FIG. 3 (main part plan view) shows a plan view when a plurality of pixels shown in FIG. 2A are arranged.

(Pixel Arrangement) As shown in Figure 2A, each pixel is connected to two adjacent scanning signal lines (gate signal line or horizontal signal line) GL and two adjacent video signal lines (drain signal line or vertical signal line). Signal line)
Within the intersection area with DL (within the area surrounded by four signal lines)
It is located in Each pixel is a thin film transistor TPT,
It includes a pixel electrode ITO1 and an additional capacitor Cadd. The scanning signals 1iGL extend in the column direction, and a plurality of scanning signals 1iGL are arranged in the row direction.

The video signal lines DL extend in the row direction, and a plurality of video signal lines DL are arranged in the column direction.

(Overall panel cross-sectional structure) As shown in FIG. 2B, a thin film transistor TPT and a transparent pixel electrode ITOI are formed on the lower transparent glass substrate 5UBI side with respect to the liquid crystal layer LC, and the upper transparent glass substrate 5
On the UBZ side, a color filter FIL and a light-shielding black matrix pattern BM are formed. The lower transparent glass substrate 5UBl side is 1, for example, 1.1 [IIn+1
It is made up of a certain thickness.

The central part of Figure 2B shows a cross section of one pixel,
The left side shows a cross section of the left edge portion of the transparent glass substrates 5UBI and 5UB2 where external lead wiring is present.

The right side shows a cross section of the right edge portion of the transparent glass substrates 5UBI and 5UB2 where no external lead wiring is present.

The sealing material SL shown on the left and right sides of FIG. 2B is configured to seal the liquid crystal LC, and the liquid crystal sealing opening (
Transparent glass substrates 5UBI and 5 excluding (not shown)
It is formed along the entire circumference of UB2. The sealing material SL is made of, for example, epoxy resin.

The common transparent pixel electrode ITO2 on the side of the upper transparent glass substrate 5UB2 is connected at least in one place to an external lead wiring formed on the side of the lower transparent glass substrate 5UBI with a silver paste material SIL. , are formed in the same manufacturing process as each of the gate electrode GT, source electrode SDI, and drain electrode SD2 described above.

Alignment films 0RII and 0RI2, transparent pixel electrode To, common transparent pixel electrode IT○, protective films PSVI and PSV2,
Each layer of the insulating film GI is formed inside the sinyl material SL. The polarizing plate POL has a lower transparent glass substrate 5UBI,
It is formed on each outer surface of the upper transparent glass substrate 5UB2.

The liquid crystal LC has a lower alignment film 0R that sets the direction of the liquid crystal molecules.
II and the upper alignment film 0RI2, and sealed by a sealing portion SL.

The lower alignment film 0RII is formed on the protective film PSVI on the side of the lower transparent glass substrate 5UBI.

On the inner surface (liquid crystal side) of the upper transparent glass substrate 5UB2, a light shielding film BM, a color filter FIL, and a protective film PSV are provided.
2. A common transparent pixel electrode (COM) IrO2 and an upper alignment film 0RI2 are sequentially laminated.

This liquid crystal display device has a lower transparent glass substrate 5UBl side,
Each layer on the upper transparent glass substrate 5UB2 side is formed separately, and then the upper and lower transparent glass substrates 5UBI and 5UB2 are formed separately.
It is assembled by overlapping the two and sealing the liquid crystal LC between them.

(Thin Film Transistor TPT> The thin film transistor TPT operates such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and drain becomes small, and when the bias is reduced to zero, the channel resistance becomes large.

The thin film transistor TPT of each pixel has three
It is divided into two (plurality) of thin film transistors (divided thin film transistors) TFT1, TFT2, and TFT3. Each of the thin film transistors TPTI to TFT3 has substantially the same size (channel length and width are the same).

Each of the divided thin film transistors TPT1 to TFT3 mainly includes a gate electrode GT, a gate insulating film GI, i
It is composed of an amorphous Si semiconductor layer As (intrinsic, not doped with conductivity type determining impurities), a pair of source electrode SDI and drain electrode SD2. Note that the source and drain are originally determined by the bias polarity between them, and in the circuit of this display device, the polarity is reversed during operation, so it should be understood that the source and drain are interchanged during operation. It is expressed by fixing the source and the other as the drain.

(Gate Electrode GT> As shown in detail in FIG. 4 (a plan view depicting only the layers gl, g2, and As in FIG. 2A), the gate electrode GT is formed in a vertical direction from the scanning signal line GL (in FIG. 2A and The gate electrode GT is configured to protrude upward (in FIG. 4) (branched into a T-shape).The gate electrode GT is configured to protrude to the formation regions of the thin film transistors TPTI to TFT3, respectively. Thin film transistor TPT1~TF
The respective gate electrodes GT of T3 are configured integrally (as a common gate electrode) and are formed continuously with the scanning signal fiGL. The gate electrode GT is formed of a single-layer first conductive film g1 so as not to form a large step in the formation region of the thin film transistor TPT. First conductive film g1
For example, a chromium (Cr) film formed by sputtering is used to have a film thickness of about 1000 [Al].

As shown in FIGS. 2A, 2B, and 4, the gate electrode GT is made thicker than the semiconductor layer AS so as to completely cover it (as viewed from below). Therefore, when a backlight BL such as a fluorescent lamp is attached below the substrate 5UBI, the opaque Cr gate electrode GT casts a shadow, and the backlight light does not shine on the semiconductor layer AS.
A conductive phenomenon, that is, deterioration of the off-characteristics of TPT due to light irradiation becomes less likely to occur. Note that the original size of the gate electrode GT is the minimum width necessary to span between the source/drain electrode SDI and Sn2 (including the alignment margin between the gate electrode and the source/drain electrode), and the width of the channel @ W
The depth length that determines the ratio to the distance (channel length) L between the source and drain electrodes, that is, the factor W/L that determines the mutual conductance gn+, is determined.

The size of the gate electrode in this embodiment is of course larger than the original size mentioned above.

Considering only the gate and light shielding functions of the gate electrode GT, the gate electrode and its wiring OL may be integrally formed in a single layer, and in this case, Si is used as the opaque conductive material.
Al containing pure At.

Also, A1 containing Pd can be selected.

(Scanning Signal Line GL> The scanning signal IGL is composed of a composite film consisting of a first conductive film gl and a second conductive film g2 provided on top of the first conductive film gl. The first conductive film gl of this scanning signal gGL is , is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is configured integrally with the first conductive film g1.The second conductive film g2 is formed using, for example, an aluminum (Afl) film shaped by sputtering, The second conductive film g2 is formed to have a film thickness of about 2000 to 4000 [Al]. It is configured so that it can be done.

Further, in the scanning signal line GL, the width of the second conductive film g2 is smaller than the width of the first conductive film g1. That is, the scanning signal line GL has a gradual step shape on its side wall.

(Gate Insulating Film GI> The insulating film GI is used as a gate I(!m film) of each of the thin film transistors TFTI to TFT3.

The insulating film GI is formed on the gate electrode GT and the scanning signal line GL. The insulating film GI is, for example, a silicon nitride film formed by plasma CVD, and is made of 3000 [Al
Form the film with a thickness of approximately

(Semiconductor Layer AS) As shown in FIG. 4, the i-type semiconductor layer As is used as a channel forming region for each of the thin film transistors TPTI to TFT3 divided into a plurality of parts.

The i-type semiconductor layer AS is made of an amorphous silicon film or a polycrystalline silicon film, and is formed to have a thickness of about 1800 [A].

This i-type semiconductor layer As is made of Si by changing the components of the supplied gas.
, N4 gate #@edge film GI are formed in the same plasma CVD equipment without being exposed to the outside from the equipment. Also, an N+ layer d doped with P for ohmic contact.

(Fig. 2B) is also continuously approximately 400 [Al thickness D
Once removed from the apparatus, the N+ layer dO and the i layer AS are patterned into independent islands using photoprocessing techniques as shown in FIGS. 2A, 2B, and 4.

The i-type semiconductor layer As is located at the intersection of the scanning signal line GL and the video signal line DL (as shown in detail in FIGS. 2A and 4).
It is also provided between both the gloss over portions. This intersection i-type semiconductor layer AS is connected to the scanning signal line O at the intersection.
It is configured to reduce short circuits between L and the video signal 1lJlDL.

(Source/drain electrode SDI, Sn2>The source electrode SD1 and the drain electrode SD2 of each of the thin film transistors TPT1 to TFT3 divided into a plurality of parts are shown in FIG. 2A, FIG. 2B, and FIG. 5 (the layer di- As shown in detail in the plan view (plan view depicting only d3), they are provided separately on the semiconductor layer As.

Each of the source electrode SDI and drain electrode SD2 is N+
3 are sequentially stacked one on top of the other from the lower layer side in contact with the type semiconductor layer clo. The first source electrode SD1! l
The electrical film d1, the second electrically conductive film d2, and the third electrically conductive film d3 are formed in the same manufacturing process as the drain electrode SD2.

The first conductive film d1 is a chromium film formed by sputtering, and has a film thickness of 500 to 1000 [A] (in this example, 6
The film thickness is approximately 0.00 [A]. When forming a chromium film thicker, the stress increases, so 2000
[The film should be formed within a range that does not exceed the thickness of a human body.

The chromium film has good contact with the N+ type semiconductor layer do. The chromium film constitutes a so-called barrier layer that prevents aluminum of the second conductive film d2, which will be described later, from diffusing into the N+ type semiconductor layer do. In addition to the chromium film, the first conductive film d1 includes a high melting point metal (Mo, Ti, Ta, W) film, and a high melting point metal silicide (M).

It may also be formed of a Si, TiSi, TaSi, WSiz) film.

After patterning the first conductive film d1 by photo processing, the N+ layer dO is removed using the same photo processing mask or using the first conductive film d1 as a mask. In other words, the portion of the N4' layer do remaining on the i-layer AS except for the first conductive film d1 is removed by the self-line.

At this time, since the N+ layer dO is etched so that its entire thickness is removed, the i MAS is also slightly etched on its surface, but the extent can be controlled by the etching time.

Thereafter, the second conductive film d2 is formed to a thickness of 3,000 to 4,000 [A] (in this embodiment, a film thickness of about 3,000 [:A]) by spun silling of aluminum. The aluminum film has less stress than the chromium film, can be formed thicker, and is configured to reduce the resistance values of the source electrode SDI, drain electrode SD2, and video signal line DL. The second conductive film d2 may be other than an aluminum film.

It may be formed of an aluminum film containing silicon (SL) or copper (Cu) as an additive.

After patterning the second conductive film d2 using a photoprocessing technique, a third conductive film d3 is formed. This third conductive film d3 is formed by sputtering and has a transparent conductivity of 1000 to 2000 [
A] (in this example, the film thickness is about 1200 [in]). This third conductive film d3 is connected to the source electrode S
It constitutes the DI, drain electrode SD2, and video signal line DL, and also constitutes the transparent pixel electrode ITOI.

First conductive film d1 of source electrode SDI, drain electrode SD
Each of the two first conductive films d1 extends further inward (into the channel region) than the upper second conductive film d2 and third conductive film d3.

In other words, the first conductive film di in these parts is the layer d
2. The configuration is such that the gate length of the thin film transistor TPT can be defined independently of d3.

As described above, the source electrode SDI is connected to the transparent pixel electrode IT.
Connected to OI. The source electrode SDI has a step shape of the i-type semiconductor layer AS (the thickness of the first conductive film g1, the thickness of the N+ layer d
It is configured along a step corresponding to the sum of the film thickness of O and the film thickness of the i-type semiconductor layer AS. Specifically, the source electrode SDI includes a first conductive film d1 formed along the step shape of the i-type semiconductor layer AS, and a first conductive film d1 formed along the step shape of the i-type semiconductor layer AS.
1, a second conductive film d2 is formed on the side connected to the transparent pixel electrode ITOI in a smaller size than that of the second conductive film d2, and a third conductive film connected to the first conductive film d1 exposed from the second conductive film. d3. Source electrode SDI
The second conductive film d2 of the first conductive film di cannot be formed thickly due to increased stress and cannot overcome the stepped shape of the i-type semiconductor layer AS.
It is configured to overcome AS. In other words, the second
The conductive film d2 is formed thick to improve step coverage. Since the second conductive film d2 can be formed thickly, it greatly contributes to reducing the resistance value of the source electrode SDI (the same applies to the drain electrode SD2 and the video signal line DL). Since the third conductive film d3 cannot overcome the step shape caused by the i-type semiconductor layer AS of the second conductive film d2, by reducing the size of the second conductive film d2, the exposed first conductive film di Not only are they configured to connect and have good adhesion, but the stepped shape of the connecting portion between them is small, so they can be connected reliably.

(Pixel electrode work TOI> The transparent pixel electrode ITOI is provided for each pixel and constitutes one of the pixel electrodes of the liquid crystal display section.The transparent pixel electrode ITOI is a thin film transistor TPTI divided into a plurality of 5 pixels. It is divided into three transparent pixel electrodes (divided transparent pixel electrodes) El, E2, and E3 corresponding to each of the TFTs 3. The transparent pixel electrodes E1 to E3 are each connected to the source electrode SDI of the thin film transistor TPT. .

Each of the transparent pixel electrodes El-E3 is patterned to have substantially the same area.

In this way, by dividing the thin film transistor TPT of one pixel into a plurality of thin film transistors TFTI-TFT3, and connecting each of the plurality of divided transparent pixel electrodes E1 to E3 to each of the plurality of divided thin film transistors TPT1 to TFT3. , even if the pixel as a whole is not a point defect (TFT2 and TFT3 are not defective), the probability of a point defect can be reduced and the defect can be made difficult to see.

Further, by configuring each of the divided transparent pixel electrodes E1 to E3 of the pixel to have substantially the same area, each of the transparent pixel electrodes E1 to E3 and the common transparent pixel electrode IT○2 can be configured. The liquid crystal capacitance (Cpix) can be made uniform.

(Protective Film PSVI> A protective film PSVI is provided over the thin film transistor TPT and the transparent pixel electrode IrO2.

The protective film PSVI is mainly formed to protect the thin film transistor TPT from moisture, etc., and a film having high transparency and good moisture resistance is used.

The protective film PSVI is made of, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD, and has a film thickness of 8000 [
Formed with a film thickness of approximately A.

(Light-shielding film BM> A shielding film BM is provided on the upper substrate 5UBZ side to prevent external light (light from above in FIG. 2B) from entering the i-type semiconductor layer AS used as a channel formation region, The pattern is as shown by the hatching in Fig. 6.In addition, Fig. 6 shows the IT○ film layer d3 in Fig. 2A,
FIG. 2 is a plan view depicting only a filter layer FIL and a light shielding film BM.

The light shielding film BM is formed of, for example, an aluminum film, a chromium film, or the like, which has a high light shielding property.

In this example, the chromium film was sputtered at 1300 [
It is formed to a film thickness of approximately A].

Therefore, the common semiconductor layer AS of TPT1 to TPT3 is made into a sandwich by the upper and lower light shielding films BM and the thick gate electrode GT, and that part is not exposed to external natural light or backlight light. The light shielding film BM is formed around the pixel as shown by the hatched area in FIG. There is. Therefore, the outline of each pixel becomes clear due to the light shielding film BM, and the contrast is improved. In other words, the light shielding film BM is a semiconductor/
It has two functions: light shielding for 1lAs and black matrix.

In addition, the backlight is attached to the 5UB2 side, and the 5UBI
can also be set as the observation side (externally exposed side).

(Common electrode ITO2> The common transparent pixel electrode ITO2 is connected to the lower transparent glass substrate 5U.
Opposing the transparent pixel electrode ITOI provided for each pixel on the BI side, the optical state of the liquid crystal changes in response to the potential difference (electric field) between each pixel electrode IT○1 and the common electrode IrO2.

This common transparent pixel electrode ITO2 has a common voltage vcO
It is configured so that I11 is applied. The common voltage Vcom is a low level driving voltage Vdm1n applied to the video signal line DL and a high level driving voltage Vdm
This is the intermediate potential between ax and ax.

(Color Filter FIL> The color filter FIL is configured by coloring a dyed base material made of a resin material such as an acrylic resin with a dye.

The color filter FIL is formed in a dot shape for each pixel at a position facing the pixel (Fig. 7), and is colored differently (Fig. 7 shows only the third conductive film layer d3 and the color filter MFIL in Fig. 3). (The R, G, and H filters are each 45' x 135°, with cross hatches). As shown in FIG. 6, the color filter FIL is formed thick so as to cover the entire pixel electrode ITOI (El-E3), and the light shielding film BM overlaps the color filter FIL and the edge portion of the pixel electrode ITOI. It is formed inside the peripheral edge of the pixel electrode ITO1.

Color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate 5UB2, and the dyed base material other than the red filter formation area is removed using photolithography technology. Thereafter, the dyed base material is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing similar steps.

The protective film PSV2 is provided to prevent the dyes used to dye the color filter FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is made of, for example, a transparent resin material such as acrylic resin or epoxy resin.

(Pixel Arrangement) As shown in FIGS. 3 and 7, a plurality of pixels of the liquid crystal display section are arranged in the same column direction as the direction in which the scanning signal line GL extends, and pixel columns Xi, X2°X3 ．． X4. It constitutes each of... Each pixel column X1, X2. X3. X4
．． Each pixel of... is a thin film transistor TFTI~
The TFT 3 and the transparent pixel electrodes E1 to E3 are arranged in the same position. That is, odd numbered pixel columns Xi, X3 .・・・
・Each pixel is a thin film transistor TPTI~TFT
The transparent pixel electrodes El to E3 are arranged on the left side, and the transparent pixel electrodes El to E3 are arranged on the right side. Odd pixel columns Xi, X3.・・・
. . , adjacent even-numbered pixel columns in the row direction X2. X4.・・・
The pixels of each of the odd-numbered pixel columns Xi, X3 . . . . each pixel is made up of pixels that are symmetrically turned upside down with respect to the extending direction of the video signal IDL. That is, pixel row X2. X4. In each pixel, thin film transistors TPTI to TFT3 are arranged on the right side, and transparent pixel electrodes E1 to E3 are arranged on the left side.

Then, pixel row X2. X4. Each pixel in pixel rows Xi, X3 . . . are moved (shifted) by half a pixel interval in the column direction. In other words, the interval between each pixel in pixel row X is 1.0 (1,0 pitch)
Then, in the next pixel column X, each pixel interval is 1.0, and with respect to the previous pixel column
, 5 pitches) is off.

The video signal line DL extending in the row direction between each pixel is configured to extend in the column direction by a half pixel interval (0.5 pitch) between each pixel column X.

As a result, as shown in FIG. 7, the pixels in the previous pixel row The pixels on which the same color filter is formed (for example, the pixel on which the red filter R of the pixel row becomes. Color filter FIL
The triangular arrangement structure of RGB can improve the mixing of each color, thereby improving the resolution of a color image.

Moreover, since the video signal gDL extends in the column direction by only half a pixel interval between each pixel column X, it does not intersect with the adjacent video signal line DL. Therefore, the video signal line D
It is possible to eliminate the routing of L and reduce its occupied area, and it is also possible to eliminate the detour of the video signal line DL and eliminate the multilayer wiring structure.

(Equivalent circuit of entire display panel) FIG. 8 shows an equivalent circuit of this liquid crystal display device.

XiG, Xi+IG, . . . are video signal lines DL connected to pixels in which the green filter G is formed.

XiB, Xi+IB, . . . are video signal lines DL connected to the pixels in which the blue filter B is formed.

Xi+IR, Xi+2R, . . . are video signal lines DL connected to pixels in which the red filter R is formed. These video signals mDL are selected by a video signal opening circuit. Yi is a scanning signal line GL that selects the pixel column X1 shown in FIGS. 3 and 7.

Similarly, Yi+1. Yi+2. Each of the pixel rows X2 . X3. . . . is a scanning signal line GL that selects each of the following. These scanning signals! GL is connected to a vertical scanning circuit. Cadd indicates additional capacitance, and Vcom indicates common voltage.

(Structure of additional capacitance Cadd) Each of the transparent pixel electrodes E1 to E3 is a thin film transistor T.
It is bent into an L-shape so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to PT. As is clear from FIG. 2C, this superposition is such that each of the transparent pixel electrodes E1 to E3 is connected to one electrode PL.
2, and a storage capacitor element (electrostatic capacitor element) Cadd is configured in which the adjacent scanning signal line OL is the other electrode PLI. The dielectric film of this storage capacitor element Cadd is an insulating film G used as a gate insulating film of the thin film transistor TPT.
It is composed of the same layer as I.

As is clear from Fig. 4, the holding capacity/amount Cadd is
It is formed in the part where the width of the first layer g1 of the gate line OL is widened. Note that the layer g1 in the portion intersecting with the drain line DL
is made thin to reduce the probability of short circuit with the drain line.

Similar to the source electrode SDI, a portion between each of the transparent pixel electrodes E1 to E3 and the capacitor electrode g (gl), which are overlapped to form the storage capacitor element Cadd, is provided with An island region made up of the first conductive film di and the second conductive film d2 is provided to prevent the transparent pixel electrode ITOI from disconnecting. This island region is configured to be as small as possible so as not to reduce the area (aperture ratio) of the transparent pixel electrode ITO↓.

(Equivalent circuit of additional capacitance Cadd and its operation) An equivalent circuit of the pixel shown in FIG. 2A is shown in FIG. 9. In FIG. 9, Cgs is the gate electrode GT of the thin film transistor TPT.
and a parasitic capacitance formed between the source electrode SD1.

The dielectric film of the parasitic capacitance Cgs is an insulating film GI. Cpi
x is a liquid crystal capacitance formed between the transparent pixel electrode IT○1 (PIX) and the common transparent pixel electrode IT○2 (COM). The dielectric film of the liquid crystal capacitor Cpix is a liquid crystal LC1 protective film psvl and an alignment film ORI. It is ORI 2.

vlc is the midpoint potential.

The storage capacitor element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) V lc when the TFT switches.

Expressing this situation using the formula, ΔV lc = ((Cgs/ (Cgs+Cadd+
Cpix)) XΔVg. Here, ΔV1c is ΔV
It represents the change in midpoint potential due to g. This change ΔVl
c causes the DC component applied to the liquid crystal, but the holding capacity C
The larger add is, the smaller the value can be.

In addition, the holding capacitor Cadd also has the effect of lengthening the discharge time, so that video information is stored for a long time after the TPT is turned off. Reducing the DC component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce so-called burn-in, in which the previous image remains when switching liquid crystal display screens.

As described above, since the gate electrode GT is made large enough to completely cover the semiconductor device S, the source/drain electrodes SD1 . The overlap area with SD2 increases, the parasitic capacitance JtCgs increases, and the midpoint potential V1c becomes closer to the gate (
This has the opposite effect of becoming more susceptible to the influence of the scanning signal Vg. However, by providing the holding capacitor Cadd, this disadvantage can also be eliminated.

The storage capacitance of the storage capacitor element Cadd is 4 to 8 times the liquid crystal capacitance Cpix (4・Cp
ix (Cadd<8・Cpix), superposition capacitance Cg
8 to 32 times (LCgs<Cadd<32・
Cgs).

(Connection method of additional capacitance Cadd electrode line) The final stage scanning signal line GL (or first stage scanning signal, 1ilGL), which is used only as a capacitance electrode line, is connected to the common transparent pixel electrode (Vcom) as shown in FIG. ) Connect to IT○2. As shown in FIG. 2B, the common transparent pixel electrode IT○2 is connected to an external wiring at the peripheral edge of the liquid crystal display device by means of a silver paste material SL. Moreover, some of the conductive layers (gl and g2) of this external lead wiring are formed in the same manufacturing process as the scanning signal line OL. As a result, the final stage capacitor electrode line OL can be easily connected to the common transparent pixel electrode ITO2.

Alternatively, as shown by the dotted line in FIG. 8, the capacitor electrode line OL at the final stage (first stage) may be connected to the scanning signal iGL at the first stage (last stage). Note that this connection can be made by internal wiring within the liquid crystal display section or external wiring.

(DC cancellation by additional capacitance Cadd scanning signal) This liquid crystal display device is based on the DC cancellation method (DC cancellation method) described in Japanese Patent Application No. 62-95125 previously filed by the applicant of the present invention. Diagram (time chart)
As shown in FIG. 2, by controlling the opening voltage of the scanning signal @DL, the DC component applied to the liquid crystal LC can be further reduced. In FIG. 10, Vi is the drive voltage of an arbitrary scanning signal line OL, and V i +1 is the drive voltage of the next stage scanning signal iGL. Vee is the scanning signal line GL
Low-level opening voltage V d min, V
dd is a high-level drive voltage Vdmax applied to the scanning signal line GL. Voltage change amount ΔV□~Δv of midpoint potential Via (see Figure 9) at each time 1=11~t
4 becomes as follows.

1=1. :ΔVz= (Cgs/C)・V21=L2
:ΔV2=+(Cgs/C)(V1+V2)-(Cad
d/C)・V2 1=13:ΔV3=-(Cgs/C)・V1+(Cad
d/C)・(V1+V2) 1=14:ΔV4= (Cadd/C)・Vl, total pixel volume fik:C= Cgs+ Cpix+
add Here, if the driving voltage applied to the scanning signal line GL is sufficient (see Note below), the DC voltage applied to the liquid crystal LC is ΔV, +ΔV4= (Cadd-V 2- Cgs-V
1)/C, so Cadd-V2=CgS-
When vl, the DC voltage applied to the liquid crystal LC becomes O.

[Note 1: At time t and t2, the change in the scanning line Vi affects the midpoint potential V1c, but during the period from t2 to t, the midpoint potential Vlc is made the same potential as the video signal potential through the signal line Xi. (enough writing of video signal).

The potential applied to the liquid crystal is almost determined by the potential immediately after the TPT is turned off (the TPT off period is overwhelmingly longer than the on period). Therefore, calculation of the DC component applied to the liquid crystal during period t1
~t3 can be almost ignored, and is the potential immediately after the TPT is turned off, that is, time 1. ．． It is only necessary to consider the influence during the transition in 14.

Note that the polarity of the video signal Vi is inverted for each frame or line, and the DC component due to the video signal itself is zero.

In other words, in the DC cancellation method, the decrease due to the drawing of the midpoint potential Vlc by the superposed capacitor icgs is applied to the storage capacitor Cadd and the scanning signal line GL of the next stage (the capacitor electrode 1IIA
) can be pushed up by the opening voltage applied to the liquid crystal LC, and the DC component applied to the liquid crystal LC can be made extremely small. As a result, the life of the liquid crystal LC of the liquid crystal display device can be improved. Of course, if the gate GT is increased in size to improve the light shielding effect, the value of the storage capacitor Cadd may be increased accordingly.

FIG. 1(C) is a plan view showing wiring provided with wiring for preventing electrostatic damage. GL is a gate signal line, DL is a drain signal line, IG is a wiring for preventing electrostatic damage by shorting each gate signal line GL, and LD is each drain signal A! Electrostatic damage prevention wiring with DL short-circuited, 2 is an electrostatic damage prevention pattern, 3
is a cutting line of the lower transparent glass substrate 5UBI. Buttons 2 for preventing electrostatic damage are provided at four locations, where the wires are disconnected, and the gate signal line and drain signal line are divided into four blocks and short-circuited.

During the manufacturing process, gate signal 4! OL and drain signal line DL
are in an electrically floating state, so if static electricity invades these signal lines, for example when taking the substrate out of a CVD device that forms a passivation protective film, the gate insulating film will be destroyed and the gate signal line GL and drain signal line will be damaged. DL will be short-circuited, so before cutting the lower transparent glass substrate 5UBI from the large glass plate, remove the electrostatic damage prevention wiring l1.
AIG and ID have been established. After wiring formation is completed, cut line 3
Cut the lower transparent glass substrate 5UBI with
Separate.

Drawing (A) is a plan view of one embodiment of the electrostatic damage prevention means for the liquid crystal display device of the present invention.

Electrostatic damage prevention pattern 2 is a minute IDl as shown in Figure 1.
** marked by a pattern separated by l.

When static electricity enters, it is discharged at the convex portion 5 of the button 2.

If no electrostatic breakdown prevention means are provided, the gate insulating film will be 1
M edge destruction occurred due to static electricity of about 00OV. In this example, when the gap between the protrusions 5 of the electrostatic damage prevention pattern 2 on each side of the electrostatic damage prevention wiring IG and ID was set to about 10 μm, static electricity was discharged with about aoov. Also, Figure 1 (
As shown in C), the electrostatic damage prevention wiring IG and ID are 4.
Since it is divided into blocks, uneven liquid crystal, disconnection and T
It is also possible to perform a conventional all-light inspection to check for PT, interlayer short circuit between gate line and drain line, etc.

In FIG. 1A, GCr is a chromium film forming a gate signal line, and DCr is an ITO (NESA) film forming a drain signal line. 4 is a cutting mark that serves as a cutting indicator.

FIG. 1(D) is a diagram showing another pattern for preventing electrostatic damage.

FIG. 1(B) is a plan view of an embodiment of the electrostatic damage prevention means for the liquid crystal display device of the present invention.

GCr is a chromium film for forming a gate signal line provided on the lower transparent glass substrate 5UBI, GI is a gate insulating film provided thereon, DCr is a chromium film for forming a drain signal line provided thereon, and DAl is a chromium film for forming a drain signal line provided thereon. The aluminum film for forming the drain signal line provided thereon, ITO, the ITO (NESA) film provided thereon for forming the transparent pixel electrode, PSV
I is a passivation protective film provided thereon.

That is, the electrostatic damage prevention pattern 2 of this embodiment is as follows.

It has a capacitive structure of lower conductive film/insulating film/upper conductive film. By forming this electrostatic damage prevention pattern 2 so that it is more easily destroyed than the gate insulating film of the portion used as the liquid crystal display section (having a smaller capacitance), when static electricity enters, the electrostatic damage can be prevented. It is possible to prevent dielectric breakdown of the prevention pattern 2 and destruction of the gate film of the liquid crystal display section.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the shape, position, constituent layers, etc. of the baton for discharging and the baton constituting the capacitor can take various configurations in addition to the above embodiments.

Furthermore, although this embodiment shows an inverted staggered structure in which gate electrode formation → gate insulating film formation → semiconductor layer formation → source/drain electrode formation, the present invention is also effective in a staggered structure in which the vertical relationship or the order of formation is reversed. be.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a means for preventing electrostatic discharge damage that can prevent electrostatic discharge damage to the edge film of the gate IIA and also perform an all-on test.

[Brief explanation of drawings]

Fig. 1 (A) is a plan view of one embodiment of the electrostatic damage prevention means for the liquid crystal display device of the present invention, and Fig. 1 (B) is a plan view of one embodiment of the electrostatic damage prevention means for the liquid crystal display device of the present invention. Plan view of embodiment FIG. 1(C) is a plan view showing wiring provided with wiring for preventing electrostatic damage. FIG. 1(D) is a diagram showing another pattern for preventing electrostatic discharge damage, and FIG. 2A is a diagram showing one pixel of the liquid crystal display section of an active matrix color liquid crystal display device which is Embodiment 2 of the present invention. FIG. 2B is a sectional view of the portion taken along the line IIB-IIB in FIG. 2A and the area around the seal portion. FIG.
FIG. 3 is a plan view of a main part of a liquid crystal display section in which a plurality of pixels shown in FIG. 2A are arranged; FIGS. 4 to 6 are a cross-sectional view taken along the NC-MC cutting line in FIG. 2A; 7 is a plan view depicting only a predetermined layer of the pixel shown in FIG. - An equivalent circuit diagram showing a liquid crystal display section of a matrix color liquid crystal display device. FIG. 9 is an equivalent circuit diagram of the pixel shown in FIG. 2A, and FIG. 10 is a time chart showing the driving voltage of the scanning signal line using the DC cancellation method. In the figure, GL...Gate signal line, DL...Drain signal line, 1... Wiring for preventing electrostatic damage, 2... Button for preventing electrostatic damage, 3... Cutting line, SUB... ...Transparent glass substrate, GL...scanning signal line, DL...video signal line, GI...insulating film, GT...gate electrode, AS...
・I-type semiconductor layer, SD...source electrode or drain electrode, PS■...protective film, LS...light shielding film, LC...
・Liquid crystal, TPT...thin film transistor, ITO...
Transparent electrode, g+d...conductive film, Cadd...holding capacitor element, Cgs...superposition capacitance, Cpix...
This is the liquid crystal capacity (numerical subscripts after letters are omitted). Figure 1 Figure 9 Figure 10 Figure 1 t2 t5t4

Claims (1)

[Claims] 1. A liquid crystal display characterized in that a part of the wiring in which each scanning signal line is short-circuited and a part of the wiring in which each video signal line is short-circuited are close to each other with a small gap in between. Measures to prevent electrostatic damage to display devices. 2. Prevention of electrostatic discharge damage in a liquid crystal display device characterized in that a part of the wiring in which each scanning signal line is short-circuited and a part of the wiring in which each video signal line is short-circuited are overlapped with each other with an insulating film interposed therebetween. means.