JPH0356172U - - Google Patents
Info
- Publication number
- JPH0356172U JPH0356172U JP11626289U JP11626289U JPH0356172U JP H0356172 U JPH0356172 U JP H0356172U JP 11626289 U JP11626289 U JP 11626289U JP 11626289 U JP11626289 U JP 11626289U JP H0356172 U JPH0356172 U JP H0356172U
- Authority
- JP
- Japan
- Prior art keywords
- multilayer wiring
- wiring boards
- ceramic multilayer
- circuit elements
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 4
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Combinations Of Printed Boards (AREA)
- Wire Bonding (AREA)
Description
第1図は本発明の一実施例の構造を示すマウン
ト平面図、第2図は従来の混成集積回路装置の構
造を示すマウント平面図である。
10……ベース・リボン、11,11a,11
b……セラミツク多層配線基板、12a,12b
……ボンデイング・ワイヤ。
FIG. 1 is a mount plan view showing the structure of an embodiment of the present invention, and FIG. 2 is a mount plan view showing the structure of a conventional hybrid integrated circuit device. 10...Base ribbon, 11, 11a, 11
b... Ceramic multilayer wiring board, 12a, 12b
...Bonding wire.
Claims (1)
散して搭載する複数個のセラミツク多層配線基板
と、前記複数個のセラミツク多層配線基板を互い
に隣接して張り付ける一枚のベース・リボンと、
前記ベース・リボン上でセラミツク多層配線基板
相互の回路素子間および回路素子と外部端子間を
それぞれ電気接続するボンデイング・ワイヤとを
含むことを特徴とする混成集積回路装置。 a plurality of ceramic multilayer wiring boards on which a required number of circuit elements required by a circuit device are distributed and mounted; a single base ribbon to which the plurality of ceramic multilayer wiring boards are attached adjacently to each other;
A hybrid integrated circuit device comprising bonding wires for electrically connecting circuit elements of the ceramic multilayer wiring boards and between circuit elements and external terminals on the base ribbon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11626289U JPH0356172U (en) | 1989-10-02 | 1989-10-02 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11626289U JPH0356172U (en) | 1989-10-02 | 1989-10-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0356172U true JPH0356172U (en) | 1991-05-30 |
Family
ID=31664544
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11626289U Pending JPH0356172U (en) | 1989-10-02 | 1989-10-02 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0356172U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005022700A (en) * | 2003-07-02 | 2005-01-27 | Seal Eitou Kk | Heat sealing device |
JP2007091344A (en) * | 2005-09-28 | 2007-04-12 | G D Spa | Automatic processing machine for products in tobacco industry and its relative controlling method |
-
1989
- 1989-10-02 JP JP11626289U patent/JPH0356172U/ja active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005022700A (en) * | 2003-07-02 | 2005-01-27 | Seal Eitou Kk | Heat sealing device |
JP4546048B2 (en) * | 2003-07-02 | 2010-09-15 | シール栄登株式会社 | Heat sealing equipment |
JP2007091344A (en) * | 2005-09-28 | 2007-04-12 | G D Spa | Automatic processing machine for products in tobacco industry and its relative controlling method |
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