JPS6450445U - - Google Patents

Info

Publication number
JPS6450445U
JPS6450445U JP14604187U JP14604187U JPS6450445U JP S6450445 U JPS6450445 U JP S6450445U JP 14604187 U JP14604187 U JP 14604187U JP 14604187 U JP14604187 U JP 14604187U JP S6450445 U JPS6450445 U JP S6450445U
Authority
JP
Japan
Prior art keywords
lengths
flat
flat package
terminals
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14604187U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14604187U priority Critical patent/JPS6450445U/ja
Publication of JPS6450445U publication Critical patent/JPS6450445U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のフラツドパツケージの一実施
例を示す部分斜視図、第2図はフラツトパツケー
ジのプリント板実装状態を示す部分斜視図、第3
図は従来のフラツトパツケージの部分斜視図、第
4図は第3図のフラツトパツケージのプリント板
への実装状態を示す部分斜視図である。 1……モールドケース、2a,2b,6……端
子、3……パツド、4……プリント板配線、5…
…絶縁塗料。
FIG. 1 is a partial perspective view showing an embodiment of the flat package of the present invention, FIG. 2 is a partial perspective view showing the flat package mounted on a printed board, and FIG.
This figure is a partial perspective view of a conventional flat package, and FIG. 4 is a partial perspective view showing the state in which the flat package of FIG. 3 is mounted on a printed board. 1...Mold case, 2a, 2b, 6...Terminal, 3...Pad, 4...Printed board wiring, 5...
...Insulating paint.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] プリント板に平面実装を行うフラツドパツケー
ジにおいて、ケースからの折曲げの長さと端子長
が異る2個の端子を交互に必要数配列したことを
特徴とするフラツトパツケージ。
A flat package for flat mounting on a printed circuit board, characterized in that two terminals having different bending lengths from the case and different terminal lengths are alternately arranged in the required number.
JP14604187U 1987-09-24 1987-09-24 Pending JPS6450445U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14604187U JPS6450445U (en) 1987-09-24 1987-09-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14604187U JPS6450445U (en) 1987-09-24 1987-09-24

Publications (1)

Publication Number Publication Date
JPS6450445U true JPS6450445U (en) 1989-03-29

Family

ID=31415168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14604187U Pending JPS6450445U (en) 1987-09-24 1987-09-24

Country Status (1)

Country Link
JP (1) JPS6450445U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4942426U (en) * 1972-07-19 1974-04-13
JPS52156564A (en) * 1976-06-22 1977-12-27 Nec Corp Semiconductor package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4942426U (en) * 1972-07-19 1974-04-13
JPS52156564A (en) * 1976-06-22 1977-12-27 Nec Corp Semiconductor package

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