JPH0355980B2 - - Google Patents
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- Publication number
- JPH0355980B2 JPH0355980B2 JP22971082A JP22971082A JPH0355980B2 JP H0355980 B2 JPH0355980 B2 JP H0355980B2 JP 22971082 A JP22971082 A JP 22971082A JP 22971082 A JP22971082 A JP 22971082A JP H0355980 B2 JPH0355980 B2 JP H0355980B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- type
- value
- graded
- barrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 239000004065 semiconductor Substances 0.000 claims description 68
- 230000004888 barrier function Effects 0.000 claims description 16
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 14
- 150000001875 compounds Chemical class 0.000 claims description 10
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 9
- 239000007769 metal material Substances 0.000 claims description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000005275 alloying Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
Description
【発明の詳細な説明】
発明の技術分野
本発明は、ヘテロ接合構造を有し、２次元電子
ガスを利用して高速動作を可能とした化合物半導
体装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an improvement in a compound semiconductor device having a heterojunction structure and capable of high-speed operation using two-dimensional electron gas.
従来技術と問題点
一般に、前記種類の化合物半導体装置として、
半絶縁性GaAs基板上にノン・ドープGaAs半導
体層、ｎ型AlxGa1-xAs半導体層を順に形成し、
表面に金・ゲルマニウム／金からなり前記ｎ型
AlxGa1-xAs半導体層とオーミツク・コンタクト
しているソース電極、ドレイン電極及び例えば
AlからなりドープAlxGa1-xAs半導体層とシヨツ
トキ・コンタクトしているゲート電極を備えた構
造が基本になつている。そして、オーミツク・コ
ンタクトしているソース電極、ドレイン電極は、
オーミツク金属と化合物半導体結晶との合金化層
を利用して前記ノン・ドープGaAs半導体層及び
前記ｎ型AlxGa1-xAs半導体層の界面に生成され
る２次元電子ガス層とコンタクトを採つているも
のである。Prior Art and Problems In general, as the above-mentioned type of compound semiconductor device,
A non-doped GaAs semiconductor layer and an n-type Al x Ga 1-x As semiconductor layer are sequentially formed on a semi-insulating GaAs substrate,
The surface is made of gold/germanium/gold and the n-type
Source and drain electrodes in ohmic contact with the Al x Ga 1-x As semiconductor layer and e.g.
The basic structure includes a gate electrode made of Al and in direct contact with a doped Al x Ga 1-x As semiconductor layer. The source and drain electrodes that are in ohmic contact are
A contact is made with the two-dimensional electron gas layer generated at the interface of the non-doped GaAs semiconductor layer and the n-type Al x Ga 1-x As semiconductor layer by using an alloy layer of an ohmic metal and a compound semiconductor crystal. It is something that is present.
然し乍ら、この従来技法に依るオーミツク・コ
ンタクトしているソース電極及びドレイン電極の
形成は、コンタクト抵抗の再現性、抵抗値及び表
面ホモロジー等の面で問題が多く、半導体装置の
VLSI化の達成を妨げる一つの要因となりつつあ
る。 However, forming source and drain electrodes in ohmic contact using this conventional technique has many problems in terms of reproducibility of contact resistance, resistance value, surface homology, etc.
This is becoming one of the factors that hinders the achievement of VLSI.
発明の目的
本発明は、前記種類の化合物半導体装置に於い
て、オーミツク金属と化合物半導体結晶とを合金
化させる技術を用いることなくオーミツク・コン
タクト電極を形成することができる技術を実現
し、この種化合物半導体装置の特性、再現性、製
造の容易性を向上するとともに高集積化が容易で
あるようにするものである。Purpose of the Invention The present invention realizes a technology capable of forming an ohmic contact electrode in the above type of compound semiconductor device without using the technology of alloying an ohmic metal and a compound semiconductor crystal, and The present invention aims to improve the characteristics, reproducibility, and ease of manufacturing of a compound semiconductor device, and to facilitate high integration.
発明の構成
本発明では、シヨツトキ金属とInxGa1-xAs半
導体結晶とのシヨツトキ障壁φBがｘ値に依存し
て小さくなることを利用し、低抵抗値で且つ再現
性が良いオーミツク・コンタクトを得ているもの
である。Structure of the Invention The present invention takes advantage of the fact that the shot barrier φ B between the shot metal and the In x Ga 1-x As semiconductor crystal decreases depending on the x value, and creates an ohmic film with a low resistance value and good reproducibility. It is something that has been contacted.
第１図はInxGa1-xAs半導体結晶に対する金
（Au）のシヨツトキ障壁φBの関係を表わす線図で
ある。 FIG. 1 is a diagram showing the relationship between the shot barrier φ B of gold (Au) and the In x Ga 1-x As semiconductor crystal.
図から判るように、或るｘ値を有しているInx
Ga1-xAs半導体結晶のシヨツトキ障壁φBが２次元
電子ガス層界面に生ずるヘテロ障壁ポテンシヤル
δに比較して小さければ表面に於けるコンタクト
抵抗Rcはヘテロ障壁ポテンシヤルに依り生ずる
抵抗Rδに比較して無視出来る程度に小さくなる。
ここで抵抗Rδは、通常、抵抗成分として働かな
い程度に小さい。 As can be seen from the figure, In x with a certain x value
If the shot barrier φB of the Ga 1-x As semiconductor crystal is smaller than the heterobarrier potential δ generated at the interface of the two-dimensional electron gas layer, the contact resistance Rc at the surface is smaller than the resistance Rδ generated due to the heterobarrier potential. It becomes so small that it can be ignored.
Here, the resistance Rδ is usually so small that it does not function as a resistance component.
然し乍ら、GaAs半導体層上に所定ｘ値を有す
るInxGa1-xAs半導体層を形成するとGaAsとInx
Ga1-xAsとの電子親和力の差及び格子ミス・マツ
チングに依り、この接合界面に新たな障壁ポテン
シヤルが生じ、コンタクト抵抗が極端に大きくな
つてしまう。 However, if an In x Ga 1-x As semiconductor layer with a predetermined x value is formed on a GaAs semiconductor layer, GaAs and In x
Due to the difference in electron affinity with Ga 1-x As and lattice mismatching, a new barrier potential is generated at this junction interface, resulting in an extremely large contact resistance.
そこで、この現象を除く為、本発明に於いては
InxGa1-xAs半導体層のｘ値をｘ＝０より徐々に
所望のｘ値まで変化させる構造（以下この構造を
グレーデツドと呼ぶ）を採用しているものであ
る。即ち、本発明ででは、InxGa1-xAs半導体層
内に生ずる障壁ポテンシヤル△（＝EC−EF）に
ついて、△≦δとなるようにｘ値を徐々に変化さ
せるようにしている。尚、ECはInxGa1-xAsの伝
導帯の電子エネルギ、EFはInxGa1-xAsのフエル
ミ準位を表わす。 Therefore, in order to eliminate this phenomenon, in the present invention,
This structure employs a structure in which the x value of the In x Ga 1-x As semiconductor layer is gradually changed from x=0 to a desired x value (hereinafter this structure is referred to as graded). That is, in the present invention, with respect to the barrier potential △ (=E C −E F ) generated in the In x Ga 1-x As semiconductor layer, the x value is gradually changed so that △≦δ. . Note that E C represents the electron energy in the conduction band of In x Ga 1-x As, and E F represents the Fermi level of In x Ga 1-x As.
ところで、シヨツトキ障壁φBが負となるまで
InxGa1-xAs半導体層に於けるｘ値を増加させる
と格子ミス・マツチングを緩和する為に必要とさ
れるInxGa1-xAs半導体層の厚みが大になるので、
半導体装置の構成上好ましくない。従つて、でき
る限りｘ値が小さい範囲で前記条件を充足する
InxGa1-xAs半導体層に於けるｘ値を設定するこ
とが肝要である。 By the way, until the shot barrier φ B becomes negative,
Increasing the x value in the In x Ga 1-x As semiconductor layer increases the thickness of the In x Ga 1-x As semiconductor layer required to alleviate lattice mismatching.
This is not preferable in terms of the structure of the semiconductor device. Therefore, the above conditions are satisfied within the range where the x value is as small as possible.
It is important to set the x value in the In x Ga 1-x As semiconductor layer.
発明の実施例
第２図は本発明一実施例の要部切断側面図であ
る。Embodiment of the Invention FIG. 2 is a cutaway side view of essential parts of an embodiment of the invention.
図に於いて、１は厚さ１〔μｍ〕のノン・ドー
プGaAs基板、２は厚さ0.03〔μｍ〕のｎ型Al0.3
Ga0.7As半導体層、３は厚さ0.03〔μｍ〕のｎ型グ
レーデツドAlxGa1-xAs（０＜ｘ＜0.3）半導体層、
４は厚さ0.05〔μｍ〕のn+型GaAs半導体層、５は
厚さ0.3〔μｍ〕のn+型グレーデツドInxGa1-xAs
（0.65＞ｘ＞０）半導体層、６は厚さ0.05〔μｍ〕
のn+型In0.65Ga0.35As半導体層（一般的に表わす
際は、n+型InyGa1-yAs半導体層とする）、７は２
次元電子ガス層、８ＳはAsからなるソース電極、
８ＤはAuからなるドレイン電極、９はアルミニ
ウムからなるシヨツトキ・ゲート電極をそれぞれ
示し、また、ここでn+は３×1018〔cm-3〕程度、
ｎは１×1018〔cm-3〕程度の不純物濃度である。
尚、本明細書では、基板及びその上の各半導体層
を含めてウエハと呼ぶことにする。 In the figure, 1 is a non-doped GaAs substrate with a thickness of 1 [μm], and 2 is an n-type Al 0.3 with a thickness of 0.03 [μm].
Ga 0.7 As semiconductor layer, 3 is an n-type graded Al x Ga 1-x As (0<x<0.3) semiconductor layer with a thickness of 0.03 [μm],
4 is an n + type GaAs semiconductor layer with a thickness of 0.05 [μm], and 5 is an n + type graded In x Ga 1-x As with a thickness of 0.3 [μm].
(0.65>x>0) Semiconductor layer, 6 has a thickness of 0.05 [μm]
n + type In 0.65 Ga 0.35 As semiconductor layer (generally expressed as n + type In y Ga 1-y As semiconductor layer), 7 is 2
Dimensional electron gas layer, 8S is a source electrode made of As,
8D indicates a drain electrode made of Au, and 9 indicates a shot gate electrode made of aluminum, where n + is approximately 3×10 18 [cm -3 ],
n is an impurity concentration of about 1×10 18 [cm −3 ].
In this specification, the term wafer includes the substrate and each semiconductor layer thereon.
本実施例に於けるソース電極８Ｓ及びドレイン
電極８Ｄ直下のエネルギ・バンド・モデルが第３
図に示されている。 The energy band model directly below the source electrode 8S and drain electrode 8D in this example is the third one.
As shown in the figure.
図に於いて、各記号は第２図について説明した
部分と同部分を指示している。 In the figure, each symbol indicates the same part as described with respect to FIG.
図から判るように、シヨツトキ障壁φB（55〔ｍ
eV〕）がヘテロ接合障壁δ（〜150〔ｍeV〕）に比
較して小さいから、低抵抗オーミツク・コンタク
ト特性が得られていることは明かである。 As can be seen from the figure, the shot barrier φ B (55 [m
Since the heterojunction barrier δ (~150 [meV]) is small compared to the heterojunction barrier δ (~150 [meV]), it is clear that low resistance ohmic contact characteristics are obtained.
第４図は他の実施例を表わす要部切断側面図で
ある。 FIG. 4 is a main part cutaway side view showing another embodiment.
図に於いて、１１はノン・ドープGaAs基板、
１２はｎ型Al0.3Ga0.7As半導体層、１３はｎ型グ
レーデツドAlxGa1-xAs（０＜ｘ＜0.3）半導体層、
１４はn+型GaAs半導体層、１５はn+型グレーデ
ツドInxGa1-xAs（0.8＞ｘ＞９）半導体層、１６は
n+型In0.8Ga0.2As半導体層、１７は２次元電子ガ
ス層、１８ＳはAuからなるソース電極、１８Ｄ
はAuからなるドレイン電極、１９はAlからなる
ゲート電極である。 In the figure, 11 is a non-doped GaAs substrate,
12 is an n-type Al 0.3 Ga 0.7 As semiconductor layer, 13 is an n-type graded Al x Ga 1-x As (0<x<0.3) semiconductor layer,
14 is an n + type GaAs semiconductor layer, 15 is an n + type graded In x Ga 1-x As (0.8>x>9) semiconductor layer, and 16 is an n + type graded In x Ga 1-x As (0.8>x>9) semiconductor layer.
n + type In 0.8 Ga 0.2 As semiconductor layer, 17 is a two-dimensional electron gas layer, 18S is a source electrode made of Au, 18D
19 is a drain electrode made of Au, and 19 is a gate electrode made of Al.
発明の効果
本発明は、AlGaAs／CaAsヘテロ接合構造を
有し、２次元電子ガスを利用して高速動作を行な
う化合物半導体装置に於いて、２次元電子ガスを
供給するAlGaAs半導体層を含むウエハ上に基板
側から順にn+型GaAs半導体層及びｎ型グレーデ
ツドInxGa1-xAs（１＞ｘ＞０）半導体層を形成
し、更に要すればその上にｎ型InyGa1-yAs半導
体層を形成し、そのｎ型グレーデツドInxGa1-x
As半導体層のｘ値、またｎ型InyGa1-yAs半導体
層を形成してある場合はｘ値及びｙ値を適宜に選
択し、ｎ型グレーデツドInxGa1-xAs半導体層或
いはｎ型InyGa1-yAs半導体層及それとコンタク
トする金属材料とのシヨツトキ障壁φB及び前記
ｎ型InxGa1-xAs半導体層内に生ずる障壁ポテン
シヤル△（EC−EF）が２次元電子ガス層界面に
生ずるヘテロ接合障壁ポテンシヤルδに比較して
φB≦δ且つ△≦δであるようにすることにより、
前記金属材料を前記ｎ型グレーデツドInxGa1-x
As半導体層或はｎ型InyGa1-yAs半導体層に被着
するのみで良好なオーミツク・コンタクトを簡単
に得ることができ、従来の如き合金化処理は全く
不要である。その結果、本発明に依る化合物半導
体装置では、ソース電極、ドレイン電極のコンタ
クト抵抗はその値が均一であり、再現性が良好で
且つ製造が容易であるから、前記種類の化合物半
導体装置を高集積化する際に適用して有効であ
る。Effects of the Invention The present invention provides a compound semiconductor device that has an AlGaAs/CaAs heterojunction structure and performs high-speed operation using two-dimensional electron gas. Then, an n + type GaAs semiconductor layer and an n type graded In x Ga 1-x As (1>x>0) semiconductor layer are formed in order from the substrate side, and if necessary, an n type In y Ga 1-y layer is formed thereon. Form an As semiconductor layer, and its n-type graded In x Ga 1-x
The x value of the As semiconductor layer, or if an n-type In y Ga 1-y As semiconductor layer is formed, the x value and y value are appropriately selected, and the n-type graded In x Ga 1-x As semiconductor layer or The shot barrier φ B between the n-type In y Ga 1-y As semiconductor layer and the metal material in contact with it and the barrier potential Δ(E C −E F ) generated within the n-type In y Ga 1-x As semiconductor layer are By making φ B ≦δ and △≦δ compared to the heterojunction barrier potential δ occurring at the interface of the two-dimensional electron gas layer,
The metal material is the n-type graded In x Ga 1-x
A good ohmic contact can be easily obtained by simply depositing it on an As semiconductor layer or an n-type In y Ga 1-y As semiconductor layer, and conventional alloying treatment is not required at all. As a result, in the compound semiconductor device according to the present invention, the contact resistance of the source electrode and the drain electrode is uniform in value, has good reproducibility, and is easy to manufacture, so that the above type of compound semiconductor device can be highly integrated. It is effective when applied to
第１図はInxGa1-xAs半導体結晶に対する金の
シヨツトキ障壁φBの関係を表わす線図、第２図
は本発明一実施例の要部切断側面図、第３図は第
２図に示した実施例のエネルギ・バンド・モデ
ル、第４図は本発明に於ける他の実施例の要部切
断側面図である。
図に於いて、１はノン・ドープGaAs基板、２
はｎ型Al0.3Ga0.7As半導体層、３はｎ型グレーデ
ツドAlxGa1-xAs（０＜ｘ＜0.3）半導体層、４は
n+型GaAs半導体層、５はn+型グレーデツドInx
Ga1-xAs（0.65＞ｘ＞０）半導体層、６はn+型
In0.65Ga0.35As半導体層（InyGa1-yAs半導体層）、
７は２次元電子ガス層、８Ｓはソース電極、８Ｄ
はドレイン電極、９はゲート電極である。
FIG. 1 is a diagram showing the relationship of gold shot barrier φ B to In x Ga 1-x As semiconductor crystal, FIG. 2 is a cutaway side view of essential parts of an embodiment of the present invention, and FIG. FIG. 4 is a cutaway side view of a main part of another embodiment of the present invention. In the figure, 1 is a non-doped GaAs substrate, 2
is an n-type Al 0.3 Ga 0.7 As semiconductor layer, 3 is an n-type graded Al x Ga 1-x As (0<x<0.3) semiconductor layer, and 4 is an n-type graded Al x Ga 1-x As (0<x<0.3) semiconductor layer.
n + type GaAs semiconductor layer, 5 is n + type graded In x
Ga 1-x As (0.65>x>0) semiconductor layer, 6 is n + type
In 0.65 Ga 0.35 As semiconductor layer (In y Ga 1-y As semiconductor layer),
7 is a two-dimensional electron gas layer, 8S is a source electrode, 8D
is a drain electrode, and 9 is a gate electrode.
Claims (1)
次元電子ガスを利用して高速動作を行なう化合物
半導体装置に於いて、２次元電子ガスを供給する
AlGaAs半導体層を含むウエハ上に基板側から順
に形成されたｎ型GaAs半導体層及びｎ型グレー
デツドInxGa1-xAs（１＞ｘ＞０）半導体層（或い
はｎ型GaAs半導体層及びｎ型グレーデツドInx
Ga1-xAs半導体層及びｎ型InyGa1-yAs半導体層）
を備え、前記ｎ型グレーデツドInxGa1-xAs半導
体層（或いはｎ型InyGa1-yAs半導体層及びｎ型
グレーデツドInxGa1-xAs半導体層）に於けるｘ
値（或いはｘ値及びｙ値）は、前記ｎ型InxGa1-x
As半導体層（或いはｎ型InyGa1-yAs半導体層）
及びそれとコンタクトする金属材料とのシヨツト
キ障壁φB及び前記ｎ型グレーデツドInxGa1-xAs
半導体層内に生ずる障壁ポテンシヤル△（＝EC
−EF）が２次元電子ガス層界面に生ずるヘテロ
接合障壁ポテンシヤルδに比較してφB≦δ且つ
△≦δであるように選択されてなることを特徴と
する化合物半導体装置。1 Has a heterojunction structure of AlGaAs/CaAs 2
Supplying two-dimensional electron gas in compound semiconductor devices that operate at high speed using dimensional electron gas
An n-type GaAs semiconductor layer and an n-type graded In x Ga 1-x As (1>x>0) semiconductor layer (or an n-type GaAs semiconductor layer and an n-type Graded In x
Ga 1-x As semiconductor layer and n-type In y Ga 1-y As semiconductor layer)
x in the n-type graded In x Ga 1-x As semiconductor layer (or the n-type In y Ga 1-y As semiconductor layer and the n-type graded In x Ga 1-x As semiconductor layer).
The value (or x value and y value) is the n-type In x Ga 1-x
As semiconductor layer (or n-type In y Ga 1-y As semiconductor layer)
and the shot barrier φ B with the metal material in contact with it and the n-type graded In x Ga 1-x As
Barrier potential △ (=E C
-E F ) is selected so that φ B ≦δ and △≦δ as compared to a heterojunction barrier potential δ occurring at the interface of a two-dimensional electron gas layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22971082A JPS59123272A (en) | 1982-12-28 | 1982-12-28 | Compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22971082A JPS59123272A (en) | 1982-12-28 | 1982-12-28 | Compound semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59123272A JPS59123272A (en) | 1984-07-17 |
| JPH0355980B2 true JPH0355980B2 (en) | 1991-08-27 |
Family
ID=16896479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22971082A Granted JPS59123272A (en) | 1982-12-28 | 1982-12-28 | Compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59123272A (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2645993B2 (en) * | 1986-06-12 | 1997-08-25 | 富士通株式会社 | Field effect type semiconductor device and method of manufacturing the same |
| US4827320A (en) * | 1986-09-19 | 1989-05-02 | University Of Illinois | Semiconductor device with strained InGaAs layer |
| KR920006875B1 (en) * | 1987-03-18 | 1992-08-21 | 후지쓰 가부시끼가이샤 | Compound semiconductor device having non-alloyed ohmic contacts |
| JPH0750781B2 (en) * | 1987-03-18 | 1995-05-31 | 富士通株式会社 | Compound semiconductor integrated circuit device |
| JPH01120871A (en) * | 1987-11-05 | 1989-05-12 | Fujitsu Ltd | Semiconductor device |
| JP2765843B2 (en) * | 1987-12-18 | 1998-06-18 | 株式会社日立製作所 | Semiconductor device |
| JPH01199475A (en) * | 1988-02-03 | 1989-08-10 | Sanyo Electric Co Ltd | Heterojunction field-effect transistor |
| JPH02232942A (en) * | 1989-03-07 | 1990-09-14 | Sony Corp | Compound semiconductor device |
| JPH05198598A (en) * | 1992-01-22 | 1993-08-06 | Mitsubishi Electric Corp | Compound semiconductor device and manufacture thereof |
| JPH06163600A (en) * | 1992-11-26 | 1994-06-10 | Nec Corp | Field-effect transistor |
-
1982
- 1982-12-28 JP JP22971082A patent/JPS59123272A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59123272A (en) | 1984-07-17 |
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