JPS60210880A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the titled device generating transmission resonance and having negative resistance by a method wherein the thickness and depth of a well are adjusted in said device with a structure that a potential well is built in by sandwiching different semiconductor layers between semiconductor materials. CONSTITUTION:A non-doped GaSb layer 22, an InAs layer 23 serving as the potential well, a non-doped GaSb layer 24 whose electrons are accelerated, and an N<+> type GaSb layer 25 to take ohmic contact are formed by lamination on an N<+> GaSb substrate 21. Next, this lamination is shaped as required by covering a necessary region with a resin mask, and by etching it; then, an electrode 26 is mounted on the uppermost layer 25. The electrode 26 is formed also on the surface of the substrate 21 exposed around the lamination. In this construction, the thicknesses of the layers 22, 23, 24, and 25 are approx. 2,000Angstrom , 100Angstrom , 2,000Angstrom , and 2,000Angstrom , respectively; thus, the characteristic of negative resistance is generated by obtaining a potential well depth of 0.83eV.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor device using negative resistance.

[Technical background of the invention and its problems]

Bipolar transistors and field effect transistors are currently widely used as semiconductor devices. Efforts are being made to increase the speed of both devices, but bipolar transistors have a minority carrier accumulation effect, and field effect transistors have limitations on the mobility of electrons or holes flowing through the channel. The current situation is that it is difficult to On the other hand, devices using negative resistance f2 are attracting attention because they are inherently suitable for increasing speed.

Gunn diodes, tunnel diodes, and the like are examples of semiconductor devices that utilize negative resistance, but the present invention described below is based on a completely different principle.

Problems with semiconductor devices that use negative resistance, which are suitable for high-speed operation, include (1) Gunn diodes.

A high electric field domain runs through the device region.

Since a single oscillation effect is performed, the power consumption increases.

On the other hand, the (21) tunnel diode has a problem in that element characteristics change due to repeated tunneling.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor device which is based on a completely different principle from that of the gun diode and tunnel diode, does not have the above-mentioned problems, and is capable of increasing speed.

[Summary of the invention]

The present invention is characterized by a structure (so-called heterojunction) in which different semiconductor materials are sandwiched between semiconductor materials as shown in FIG. With such a structure, the hand diagram of this structure can be made as shown in FIG. 2 by selecting appropriate materials. Let the depth of the potential well in FIG. 2 be VQ + the thickness L. Let us assume that an electron with energy E enters this potential well from the left. The electrons are reflected to the left of the manufacturing section and partially transmitted to the right. This transmittance T is expressed by Washiko's mechanical calculation. Here, h is the blank constant divided by 2π and 1m is the effective mass of electrons in the semiconductor. When this transmittance is plotted against the electron energy E, the result is as shown in FIG. As is clear from FIG. 3 and equation (1), when N is an integer or rewritten, the transmittance T=1. In other words, electrons incident on the well of potential from ) on the left are not affected by this potential in any way, but in other cases T<
1, and some of it is reflected to the left. Therefore, if the energy E of electrons incident on this semiconductor device can be controlled by an external voltage V, a negative resistance semiconductor device can be manufactured. This explanation will be given with reference to FIG. voltage v
1, the electron energy is E, and T=1.

Next, voltage V greater than 7 times! If the energy of the electron becomes E:, as is clear from Figure 3, T
As a result, a large amount of electrons are reflected, and fewer electrons are transmitted. Since the current is proportional to the transmittance T, the current decreases when the voltage increases.

That is, negative resistance as shown in FIG. 4 can be realized.

(2) The energy average of electrons at a larger voltage V is made larger than the energy E1 at a voltage (1).62 The size of the semiconductor device is reduced.

This can be achieved by preventing electrons from being scattered in the region Ll in FIG.

〔Effect of the invention〕

According to the present invention, a semiconductor device having negative resistance can be realized by using a heterojunction to generate transmission resonance.

[Embodiments of the invention]

The present invention will be described with reference to FIG. 5 with reference to two embodiments f using a Ga8b-InAs heterojunction. first.

A Te-doped n-Ga8b substrate 2 is prepared, a non-doped Garb layer n is laminated as described above, and an lnAs layer 1 which is to become a potential well is laminated thereon. .

Sara C: Non-doped Garb layer prisoner where Tanoko receives acceleration.

Garb l@ for making ohmic contact
25 are sequentially laminated. Such Ga8b-In
The As product li1 structure can be easily formed by molecular beam epitaxy. Next, cover the necessary areas with resist, and after etching to create an imaginary structure like the 5th south, add electrodes.

The dimensions of each layer are, for example, the non-doped Garb layer n is 2000
A', InAs layer illusion is 1O0A', 1< Ga8bm24 where the child is accelerated is 2000 A- n Garb f@2B for making ohmic contact is 200
It is assumed to be 0A'.

In this example, the depth of the potential well is 0.83
e V, and negative resistance can be achieved.

In one or more embodiments, a Garb-InAs system has been described; however, the present invention is not limited thereto, and may be applied to other semiconductors such as GaP-8i, GaA/5-Ga, etc.
It is possible to realize a semiconductor device similar to that shown in FIG. 5 by using a heterojunction structure such as A/In-containing 5-GaInAs on an As or InP substrate.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a semiconductor structure according to the present invention, and FIG. 2 is a diagram showing energy levels of the semiconductor structure. FIG. 3 is a diagram showing the electron transmittance in the semiconductor device structure C2 of the invention, FIG. 4 is a diagram showing the current-voltage characteristics of the semiconductor device of the invention, and FIG. 5 is a diagram showing the current-voltage characteristics of the semiconductor device of the invention. It is a figure showing an example. 2]: Garb substrate, 22 = non-doped Garb layer. Z3: InAs layer, 24:'&M, non-doped Garb layer whose particles undergo acceleration. 25: nGaSb#, 26: electrode. Agent Patent attorney Kensuke Norichika (and 1 other person) Figure 1 Figure 2 Figure 3 Figure @, Eolya F of ``!r Figure 4 Figure 15V- Figure 5?

Claims (1)

[Claims] Different semiconductor layers are sandwiched between semiconductor materials. A semiconductor device having a structure in which a potential well is created, characterized in that by adjusting the depth and thickness of the well, transmission resonance is produced and negative resistance is produced.