JPH0353796B2 - - Google Patents

Info

Publication number
JPH0353796B2
JPH0353796B2 JP26839585A JP26839585A JPH0353796B2 JP H0353796 B2 JPH0353796 B2 JP H0353796B2 JP 26839585 A JP26839585 A JP 26839585A JP 26839585 A JP26839585 A JP 26839585A JP H0353796 B2 JPH0353796 B2 JP H0353796B2
Authority
JP
Japan
Prior art keywords
layer
foil
double
circuit board
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP26839585A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62128596A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP26839585A priority Critical patent/JPS62128596A/ja
Publication of JPS62128596A publication Critical patent/JPS62128596A/ja
Publication of JPH0353796B2 publication Critical patent/JPH0353796B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
JP26839585A 1985-11-30 1985-11-30 リジッド型多層プリント回路基板の製造方法 Granted JPS62128596A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26839585A JPS62128596A (ja) 1985-11-30 1985-11-30 リジッド型多層プリント回路基板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26839585A JPS62128596A (ja) 1985-11-30 1985-11-30 リジッド型多層プリント回路基板の製造方法

Publications (2)

Publication Number Publication Date
JPS62128596A JPS62128596A (ja) 1987-06-10
JPH0353796B2 true JPH0353796B2 (en:Method) 1991-08-16

Family

ID=17457877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26839585A Granted JPS62128596A (ja) 1985-11-30 1985-11-30 リジッド型多層プリント回路基板の製造方法

Country Status (1)

Country Link
JP (1) JPS62128596A (en:Method)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933045A (en) * 1989-06-02 1990-06-12 International Business Machines Corporation Thin film multilayer laminate interconnection board assembly method
JP2608980B2 (ja) * 1990-09-11 1997-05-14 電気化学工業株式会社 金属板ベース多層回路基板
JP6639890B2 (ja) * 2015-12-11 2020-02-05 株式会社ダイワ工業 配線基板積層体及びその製造方法

Also Published As

Publication number Publication date
JPS62128596A (ja) 1987-06-10

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees