JPH0338777B2 - - Google Patents

Info

Publication number
JPH0338777B2
JPH0338777B2 JP57047577A JP4757782A JPH0338777B2 JP H0338777 B2 JPH0338777 B2 JP H0338777B2 JP 57047577 A JP57047577 A JP 57047577A JP 4757782 A JP4757782 A JP 4757782A JP H0338777 B2 JPH0338777 B2 JP H0338777B2
Authority
JP
Japan
Prior art keywords
circuit
frequency
output
phase
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57047577A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58164327A (ja
Inventor
Etsuro Sakamoto
Masahiko Machida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP57047577A priority Critical patent/JPS58164327A/ja
Publication of JPS58164327A publication Critical patent/JPS58164327A/ja
Publication of JPH0338777B2 publication Critical patent/JPH0338777B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/185—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using a mixer in the loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP57047577A 1982-03-25 1982-03-25 周波数逓倍回路 Granted JPS58164327A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57047577A JPS58164327A (ja) 1982-03-25 1982-03-25 周波数逓倍回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57047577A JPS58164327A (ja) 1982-03-25 1982-03-25 周波数逓倍回路

Publications (2)

Publication Number Publication Date
JPS58164327A JPS58164327A (ja) 1983-09-29
JPH0338777B2 true JPH0338777B2 (enrdf_load_stackoverflow) 1991-06-11

Family

ID=12779095

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57047577A Granted JPS58164327A (ja) 1982-03-25 1982-03-25 周波数逓倍回路

Country Status (1)

Country Link
JP (1) JPS58164327A (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6210927A (ja) * 1985-07-08 1987-01-19 Yaesu Musen Co Ltd Ｐｌｌ発振回路
JP2817676B2 (ja) * 1995-07-31 1998-10-30 日本電気株式会社 Ｐｌｌ周波数シンセサイザ
JP6094730B2 (ja) * 2012-11-07 2017-03-15 セイコーエプソン株式会社 周波数変換回路、原子発振器、電子機器及び周波数変換回路の制御方法

Also Published As

Publication number Publication date
JPS58164327A (ja) 1983-09-29

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