JPH0338777B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency multiplier circuit, and particularly to a frequency multiplier circuit whose basic configuration is a phase-locked loop (PLL), in which the frequency of an output signal can be selected in fine frequency steps.

For example, video tape recorders (VTRs) use a low-frequency conversion color signal recording method that converts the color signal to a lower frequency band and records it, but when demodulating the recorded signal to obtain a video signal, In order to prevent the cross-modulation components of the low-pass conversion color signal from becoming interference waves for the video signal, the frequency f of the low-pass conversion color signal is set so that the frequency of this interference wave is an odd multiple of 1/2 of the horizontal synchronization frequency _fH . _S is multiplied by a frequency multiplier circuit, thereby preventing crosstalk of the color signal with respect to the video signal through an interleaving effect.

However, in order to satisfy such conditions, conventionally, the frequency step width Δf that can be selected as the frequency f ₀ of the multiplied output signal can be set to the value expressed by Δf = 1/Nf _H (1). The frequency synthesizer type configuration shown in FIG. 2 is used. Here, N is an integer value.

The frequency multiplier circuit in Figure 1 uses an input signal S1 whose reference frequency is f _r (corresponds to the horizontal synchronization signal whose frequency is f _H ).
is frequency-divided by the 1/N frequency divider circuit 1 and applied to the phase comparison circuit 2 as a comparison input S2, and the comparison output S3 is applied to the voltage controlled oscillator circuit (VCO) 3 as a control voltage input. This VCO3
The output S4 is sent out as a frequency multiplied output signal, and is also frequency-divided by the 1/M frequency divider circuit 4 and fed back to the phase comparator circuit 2.
A PLL is formed. Therefore, the frequency f ₀ of the frequency multiplied output signal S4 sent out from the output terminal of the VCO 3 is f ₀ =M/ _Nfr (2).

As is clear from equation (2), the frequency of the output signal S4
In selecting the value of f ₀ , the minimum step is 1/ _Nfr (=Δf), and a value M times that value (M=1, 2, 3, . . . ) can be selected. Therefore, by arbitrarily selecting the integers N and M as necessary, the frequency-multiplied output signal S with the optimal ratio value to the reference frequency f _r can be obtained.
You can get 4.

However, according to the conventional configuration shown in FIG. 1, the comparison input S2 to the phase comparison circuit 2 is obtained by being frequency-divided in the 1/N frequency divider circuit 1, so the frequency 1/Nf _r becomes low, and therefore the phase comparison circuit 2 It is unavoidable that the S/N of the differential output S3 of the circuit 2 deteriorates. In addition, since the frequency of the comparison input S2 is low, the cutoff frequency of the loop filter provided in the PLL (for example, built in VCO3) must be lowered in order to improve the response characteristics of the PLL. There are certain limits.

In order to alleviate this problem, as shown in FIG. 2, the input signal S1 as a reference signal is directly supplied to the phase comparison circuit 5 as a comparison input, and
A configuration is used in which the output S5 of the VCO 3 is frequency-divided in a 1/N frequency divider circuit 1 and sent out as a frequency-multiplied output signal S4.

According to the configuration shown in FIG. 2, the frequency of the input signal applied to the PLL is increased to the reference signal _fr , so that the S/N ratio in the phase comparator circuit 5 is reduced.
Although the problem of deterioration of response characteristics in the loop filter of the PLL can be avoided, since the frequency of the output S5 of the VCO 3 becomes high, there is a problem that special specifications having a high operating frequency must be used as the frequency dividing circuits 1 and 4. Incidentally, since the 1/M frequency divider circuit 4 and the 1/N frequency divider circuit 1 actually have a configuration in which flip-flop circuits are connected in multiple stages and a reset loop is provided as necessary, a large number of specially designed flip-flop circuits are used. Necessary and undesirable.

The present invention takes the above points into account and effectively solves the problems of the conventional configuration.The present invention provides a plurality of phase shifters in the PLL loop, and sequentially switches the phase shifters at a predetermined period. By doing so, the frequency step width Δf can be precisely selected.

An embodiment of the present invention will be described in detail below with reference to the drawings. In FIG. 3, the input reference signal S11 is applied to the phase comparison circuit 11 as a comparison input, and the comparison output S12 is applied to the VCO 12 as a control voltage input. However, the oscillation output S1 of VCO12
3 is phase shifted through the phase shifter circuit 13 to become 1/
The signal is applied to the M frequency divider circuit 14, frequency-divided by the 1/M frequency divider circuit 14, and then fed back to the phase comparator circuit 11, thus forming a PLL.

The phase shifter circuit 13 receives the output signal S of the VCO 12.
A plurality of N phase shifters 13A receiving 13...1
3J...13N. 1st...Jth...Nth
The th phase shifter 13A...13J...13N divides the phase 2π corresponding to one period T _r of the reference signal S11 into N equal parts and obtains the phase 2π/N as a unit, and multiplies it by 1... J times... N times phase 2π/N...2π/NJ...2π/N
The phase of the output signal S13 of the VCO 12 is shifted by N.
The output of each phase shifter 13A...13J...13N is the corresponding first...J phase shifter of the changeover switch circuit 15.
...Nth input terminal 15A...15J...1
Connected to 5N.

The changeover switch circuit 15 performs a switching operation based on the reference signal S11, and switches between the first...Jth...Nth input terminals 15A... for each period of the reference signal S11.
The outputs of 15J...15N are sequentially selected and sent to the 1/M frequency dividing circuit 14 from the output terminal 15M. When this switching step operation completes one cycle, the changeover switch circuit 15
repeats this cycle from then on.

In the above configuration, the changeover switch circuit 1 of the phase shifter circuit 13 is switched in each period of the reference signal S11.
5 is the first...Jth...Nth phase shifter 13
The outputs of A...13J...13N are sequentially output. Therefore, each time the output of the phase shifter circuit 13 is switched, the VCO 12 performs a compensation operation corresponding to the amount of phase shift, and makes the difference output S12 of the phase comparator circuit 11 zero. However, the phase shifter circuit 13
The amount of change Δθ _PS in the amount of phase shift that occurs in this output S14 each time the output S14 is switched is the output signal S1
3, the phase _θ r of the comparison input S11 of the phase comparison circuit 11 and the phase θ _V of the output _S15 of the 1/M frequency dividing circuit 14
_{In the state where the relationship between _} +Δθ _PS ) ...(6) The PLL becomes locked. Therefore (5),
Substituting equation (6) into equation (4), f _r・2π・Tr ₋₁ /M(f ₀・2π・T _r +Δθ _PS )=0 ...(7) Therefore, f ₀ =Mf _r −Δθ _PS /2πT _r ...(8) From equation (3), f ₀ = Mf _r -1/Nf _r = M・N−1/N・f _r ...(9) Here, in equation (9) , the frequency f ₀ of the multiplied output signal S13 means that it is possible to obtain a frequency multiplier circuit in which 1/N _fr can be selected as the minimum step with respect to the frequency _fr of the reference signal S11.

In addition, equation (9) shows that the frequency f ₀ of the multiplied output signal S13 is in phase with respect to the frequency Mf _r obtained by the operation of the 1/M frequency dividing circuit 14 when the phase shifter circuit 13 is considered not to exist. This indicates that the frequency is lowered by 1/Nf _r by the frequency change caused by the shifter circuit 13.

Incidentally, if we consider that the phase shifter circuit 13 does not exist, θ _r = f _r・2π ・T _r ...(10) θ _v = 1/M(f ₀・2π ・T _r ) ...(11) Therefore, from equation (4), θ _r −θ _v = f _r・2π・T _r −1/M (f ₀・2π・T _r )=0 ... (12) Therefore, f ₀ = Mf _r ... (13).

Note that the frequency f ₁ of the output S14 of the phase shifter circuit 13 when the PLL is in a locked state is f ₁ =f ₀ -1/Nf _r (14) The difference between this frequency f ₁ and the frequency f _r of the reference signal S11 is The relationship is f _r =1/M·f ₁ (15).

In the above description, a case has been described in which the changeover switch circuit 15 of the phase shifter circuit 13 is repeatedly switched in the order of the first...Jth...Nth phase shifters 13A...13J...13N. On the other hand, if the switching is repeated in the order of Nth...Jth...first phase shifter 13N...13J...13A, then the amount of change in phase shift amount that occurs in the output S14 of the phase shifter circuit 13 is Δθ _PS always decreases and becomes Δθ _PS = −2π/N (16), so the value of f ₀ corresponding to equation (9) is f ₀ = Mf _r +1/Nf _r = M・N+1/N・f _r ... (17) Therefore, the frequency f ₀ of the multiplied output signal S13 is based on the 1/M frequency divider circuit 14 with the minimum step of 1/Nfr with respect to _the frequency f _r of the reference signal S11. This indicates _that the frequency obtained based on the phase shifter circuit 13 is higher than the obtained frequency Mfr by 1/ _Nfr .

Equations (9) and (17) indicate that each time the changeover switch circuit 15 switches, the output S of the phase shifter circuit 13 is
14 is shifted by Δθ _PS = ±2π/N, but in general, if the changeover switch circuit 15 is switched every Ith order in FIG. 3, then equation (9) and ( The formula for the frequency f ₀ corresponding to equation 7) is f ₀ = Mf _r −I/Nf _r = M・N−I/Nf _r ...(18) f ₀ = Mf _r +I/Nf _r = M・N+I/ Nf _r ...(19) Thus, it can be seen that it is possible to realize a frequency multiplier circuit in which the multiplier can be selected with I/Nf _r as the minimum step. By doing so, it is possible to eliminate the need to use the 1/N frequency divider circuit 1 compared to the conventional configuration shown in FIG.

When creating a low frequency conversion color signal for a VTR using a frequency multiplication circuit based on the above principle, the configuration shown in FIG. 4 can be applied. In the case of FIG. 4, the phase shifter circuit 13 is composed of a shift register circuit in which L-stage D flip-flop circuits F1, F2, . th flip-flop circuit F1
It is fed back to the D input terminal of
The oscillation output S13 (FIG. 5A) of the VCO 12 is given, thus flip-flop circuits F1 and F2
...FL is sequentially set or reset by the output S13 of the VCO 12.

The D inputs of the first, second...L-th flip-flop circuits F1, F2...FL are the first, second...L-th input terminals K1,
K2... is connected to KL, and the Lth, 1st...
...(L-1)th flip-flop circuit FL,
F1...The Q output of F(L-1) is the (L+1)th, (L+2)th...
...2nd L-th input terminal k(L+1), k(L+2)
. . . k2L, and thus the changeover switch circuit 15 switches each period according to the reference signal S11, and the input terminals k1, k2, . . . KL,
The outputs of k(L+1), k(L+2)...k2L are sequentially given to the 1/M ₁ frequency divider circuit 17, and after being frequency-divided to 1/M ₁ , the outputs are sent to the comparator circuit 11 as the feedback signal S15.
Feedback to.

In the configuration shown in Fig. 4, the output S1 of VCO12
3 causes the phase shifter circuit 13 to perform a shift operation every cycle. That is, when all the flip-flop circuits F1 to FL are in the reset state at time _t1 in FIG.
13 (FIG. 5A) is applied to the clock input terminal C, the output of the flip-flop circuit FL in the final stage at logic "H" level (FIG. 5B1 and B(L+
1)) is applied to the D input terminal of the first-stage flip-flop circuit F1, this first-stage circuit F1 is set (B2 and B(L+2) in FIG. 5), and then the second, third, and so on of the VCO 12 are set. Every time the periodic output S13 is applied to the clock input terminal C, the second, third, . . . L-th flip-flop circuits F2, .
and B(L+3)...BL and B2L). Thus, when all the flip-flop circuits F1 to FL are set at time _t2 in FIG.
Since the output of FL becomes logic “L”, from then on the (L
+1), (L+2)...2nd L cycle output S1
3 is applied to the clock input C, the first,
The second...L-th circuits F1, F2...FL are reset. When all the flip-flop circuits F1 to FL are reset in this way, the output of the circuit FL at the final stage returns to logic "H" and the round operation is completed, and this round operation is repeated thereafter.

Therefore, at time t ₁ in FIG. 5, the first, second...
When the Lth circuits F1, F2...FL are all reset by the clock S13 (Fig. 5A) obtained from the VCO 12, the The signal FL at the first input terminal K1 rises to logic "H" (B1 in Fig. 5), and from then on, the clock signal S1 is output from the VCO 12.
3 is obtained, the circuits F1, F2...FL are sequentially set, and the signal F1 of the second, third...L-th input terminals k2, k3...kL is
Q, F2Q...F(L-1)Q rises to logic "H" (B2, B3...BL in FIG. 5).

Eventually, at time _t2 , the first to Lth circuits F
When all 1 to FL are set, the Lth circuit
The signal FLQ at the (L+1)th input terminal k (L+1), which is the Q output of FL, rises to logic "H" (B (L+1) in FIG. 5), and thereafter, every time the clock signal S13 is obtained from the VCO 12, the circuit F1, F2...
...The signal F of the (L+2)th, (L+3)th...2Lth input terminal k(L+2), k(L+3)...k2L is reset by sequentially resetting FL.
1, F2...F(L-1) rises to logic "H" (Figure 5 B(L+2), B(L+3)
...B2L).

Each signal rising to the logic "H" level in this way is applied to all flip-flop circuits F1 to FL.
The VCO1 is reset (or set) one by one after completing one cycle until it reaches the set (or reset) state.
When L times of the period _T1 of the output S13 of No. 2 have elapsed, the output S13 sequentially falls to the "L" level. Thus, the signals FL of each input terminal k1, k2...k2L,
F1...F(L-1) is the output S1 of VCO12
3 divided by a fractional ratio 1/2L corresponding to twice the number of stages L of the flip-flop circuit of the phase shifter circuit ₁₃ , and has a phase corresponding to one period _T1 of the output S13 of the VCO 12 in sequence. The phase is sequentially shifted by an amount (2π/2L, which is the value obtained by equally dividing the phase 2π of one period of each signal divided by 2L into 2L).

Therefore, in the case of the embodiment shown in FIG. 4 as well, the multiplied frequency output S20 having a frequency f ₀ that can be expressed by a general formula similar to the formulas (18) and (19) as described above with respect to the principle configuration of FIG. (Fig. 5C) can be obtained.

f ₀ =M ₁・2L+I/2Lf _r ...(20) Here, in the case of FIG. 4, the phase shifter circuit 13 is
Since 2L shift signals FL to F(L-1)Q, which are sequentially phase-shifted by 2π/2L and frequency-divided by 1/2L, are output, the frequency f ₀₁ of the output S13 of the VCO 12 is the frequency of the reference signal S11. It has a frequency f ₀₁ = ( _{M 1 2L} + I) f _r (21) which is M 1.2L times as large as f r, but this output f ₀₁ is divided into 1/2L in the phase shifter circuit 13 _. .

When applying the frequency multiplier circuit with the configuration shown in Figure 4 to a VTR, in the two-frequency method, M ₁ = 44, 2L = 8, I = +1 or -1 should be selected in equation (20); In this case, the frequency f ₀ of the frequency multiplied output S20 is f ₀ =(44±1/8)·f _H (22). Also, in the case of the PI method, in equation (20),
M ₁ = 44, 2L = 4, I = 1, or M ₁ =
44, 2L=8, and I=2, and the frequency f ₀ of the frequency multiplied output S20 in this case becomes f ₀ =(44-1/4)f _H (23).

With the configuration shown in FIG. 4, it is possible to realize a frequency multiplier circuit in which the multiplier can be selected in fine steps with I/2Lf _r as the minimum step. As in this embodiment, the phase shifter circuit 13 can be constructed by simply cascading a plurality of flip-flop circuits and dividing the frequency by ^2x (with a feedback loop for resetting the circuit midway). Therefore, flip-flop circuits F1 to FL that operate at low speed can be used. Incidentally, if a high-speed flip-flop circuit must be used, the stray capacitance existing in the circuit cannot be ignored, so a large current drive power supply must be prepared to charge it. There's no need to be like that. Furthermore, if configured as shown in FIG. 4, the input of the 1/ _M1 frequency divider circuit 17 divides the output of the VCO 12 by 1/2L, so this frequency divider circuit 17 can also be configured with a low-speed flip-flop circuit.

In the case of FIG. 4, a circuit that divides the frequency of the phase shift output with respect to the input signal is used as the phase shifter circuit 13, but any circuit that can shift the phase may be used.

Further, in the above description, a case has been described in which the changeover switch circuit 15 is switched by the reference signal S11, but the present invention is not limited to this, and the point is that the switch circuit 15 may be switched at a predetermined cycle.

As described above, according to the present invention, since the comparator circuit can be operated at a high frequency, it is possible to obtain a frequency multiplier circuit with high responsiveness for the PLL. It is possible to select a fine frequency step width as necessary without having to insert the frequency step.

[Brief explanation of drawings]

1 and 2 are block diagrams showing a conventional frequency multiplier circuit, FIG. 3 is a block diagram showing the principle configuration of a frequency multiplier circuit according to the present invention, and FIG. 4 is a block diagram showing a specific embodiment thereof. , FIG. 5 is a signal waveform diagram for explaining the operation. 1...1/N frequency divider circuit, 2, 5...phase comparison circuit 3
...voltage controlled oscillator circuit (VCO), 4...1/M frequency divider circuit, 11...phase comparison circuit, 12...VCO, 13...
Phase shifter circuit, 13A to 13N...phase shifter,
14...1/M frequency divider circuit, 15...changeover switch circuit, 17...1/M ₁ frequency divider circuit.

Claims (1)

[Claims] 1. A phase comparison circuit that compares the phases of an input signal and a feedback signal, a voltage controlled oscillation circuit that generates an output at a frequency corresponding to the difference output of this phase comparison circuit, and this voltage controlled oscillation circuit. and a frequency dividing circuit that divides the output of the voltage controlled oscillator at a predetermined frequency division ratio and feeds it back to the phase comparison circuit as the feedback signal, wherein A frequency multiplier circuit characterized in that a phase shifter circuit in which a phase shift amount sequentially changes at a predetermined cycle is provided in a loop. 2. The frequency multiplier circuit according to claim 1, wherein the phase shifter circuit changes the amount of phase shift with the cycle of the input signal.