JPH01133420A - Phase locked loop - Google Patents

Abstract

PURPOSE:To lower the voltage level of the AC component of error signals and make the time constant of a loop filter smaller so as to reduce occurrence of jitters, by providing a means which multiplicatively increases the AC component of phase-compared error signals like frequencies. CONSTITUTION:When a reference signal e1(t) is inputted to a phase dividing circuit 2 from an input terminal 1, phase dividing output signals e1(t)-e4(t) are respectively supplied to phase comparators 3-6 from the circuit 2. When the output signal of a voltage-controlled oscillator(VCO) 10 is inputted to a phase dividing circuit 7, on the other hand, phase dividing output signals e5(t)-e8(t) are respectively supplied to the phase comparators 3-6 from the circuit 7. Therefore, at the phase comparator 3 phase comparison is performed by multiplying the signal e1(t) by the signal e5(t) and a phase comparing output signal e9(t) is outputted. Similarly, phase comparing output signals e10(t)-e12(t) are respectively outputted from the phase comparators 4-6. These signals are supplied to an adder circuit 8 where they are added to each other. The output signal e13(t) of the circuit 8 is supplied to the VCO 10 as an error signal through a loop filter 9.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a phase-locked loop, and more particularly to a phase-locked loop capable of reducing jitter in a voltage controlled oscillator (VCO).

(Background of the Invention) In power line transmission of data, the data modem
When multiplying the power supply frequency using a phase-locked loop (hereinafter abbreviated as PLL) due to frequency synchronization and the need to perform frequency multiplication and phase synchronization, the PLL increases VCO jitter as the multiplication number increases. This will also increase and become a problem. The present invention addresses this problem and devises a method to systematically improve it.

(Conventional technology) The PLL performs modulation and reversal w14. Signal tracking.

It is widely applied to automatic frequency control, signal period, narrowband filter, etc.

Its basic principle is a phase comparator, a loop filter (LF)
It is composed of a phase locked loop (PLL) consisting of a VCO and a VCO, and performs a phase comparison between the input signal and the output signal of the
The phase error signal is converted into an error voltage via a loop filter, and the voltage is supplied to the vCO to control the oscillation frequency (phase), thereby performing phase synchronization.

(Problem to be solved by the invention) In PLL, temporary phase error (generally called jitter) of vCO, that is, jitter, tends to be a problem in frequency multiplication using PLL, and the number of multiplication increases. jitter increases accordingly. This is because, especially when the input signal frequency is low, the time constant of the loop filter becomes large, and the influence of 1/f noise in the VCO transistor reaches outside the loop band in terms of frequency. Therefore, in order to suppress this jitter, it is necessary to widen the loop band, but on the other hand, the AC component of the error signal becomes impossible to ignore (this is because the time constant of the loop filter is small). Therefore, the oscillation frequency of the VCO is angularly modulated by the alternating current component, which poses a problem. In other words, the conventional PL
L has a problem in which the jitter problem and the modulation problem are caught in the middle when performing frequency transmission.

Therefore, an object of the present invention is to provide a PLL that can improve the problems of the above-mentioned conventional technology.

(Means for Solving the Problems) In order to achieve the above object, the present invention supplies an input signal to a phase comparator, supplies an output signal of a voltage controlled oscillator to the phase comparator, and supplies the input signal to the phase comparator. In the phase-locked loop, the error signal output from the phase comparator is converted into an error voltage via a loop filter, and is supplied to the voltage controlled oscillator. A voltage controlled oscillator that supplies a first plurality of phase output signals divided into a plurality of phases at intervals to each of the divided number of phase comparators, and whose phase is shifted by π/2 from the first plurality of phase output signals. A second plurality of phase output signals obtained by dividing the output signal of the first plurality of phase output signals into a plurality of phases equally spaced within a range of 2π corresponding to each of the first plurality of phase output signals are divided into the first plurality of phase output signals. to each of the phase comparators supplied with corresponding phase output signals of the first plurality of phase output signals and the second plurality of phase output signals of the first plurality of phase output signals.
perform phase comparison with multiple phase output signals of
A phase locked oscillator characterized in that an error signal obtained by adding a plurality of phase comparison output signals outputted from each of the phase comparators is converted into an error voltage via a loop filter and supplied to the voltage controlled oscillator.・It provides a loop.

(Embodiment) An embodiment of the PLL according to the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the basic configuration of a PLL according to the present invention.

In Fig. 1, reference signal e is input from input terminal 1.
+ (U is supplied to the phase division circuit 2. The reference signal e + (j) is e + (t) - A cos (ωt + 01 (t))
' It is shown in (1).

The output signal of the phase division circuit 2 is a plurality of signals with different phases (that is, a signal divided into a plurality of phases at equal intervals within a range of 2π), but here, four phase signals are output. ing. That is, e + (i) shown in equation (1) is output as is as the output of a of the phase division circuit 2. Next, the output e2 (t) of b is e 2 (t) −A Cog((lc) t−−+θ
+ ([)) ■ is output. Next, the output e of C
s (t) is e s (t) −Acos(ωt
−−10+ (1)) ■ is output. Furthermore, d
The output e 4 (j) is e 4 (t) = Acos
(ωt −□ π〇 +(t)) (4) is output.

Then, the phase division output signal e + (i) is sent to the multiplier type phase comparator 3, the same < 82 (t) is sent to the phase comparator 4, the same < e 3 (t) is sent to the phase comparator 5, and the same < 84 (j) are respectively supplied to the phase comparator 6.

On the other hand, the output signal of the V CO 10 is supplied to a phase division circuit 7, and the output signal of the phase division circuit 7 is divided into a plurality of signals having different phases (that is, a signal divided into a plurality of phases at equal intervals within a range of 2π). Here, four phase signals are output. That is, the output e 5 (0) of phase division circuit 7 (a) is e 5 (t) −A sin (ωt+02 (t))
(5) is output. Next, similarly, the output e e (t) in (b) is expressed as e a (j) −A sin(ωt −−+02(t
)) 03) is output. Next, similarly (C)
The output e 7 (t) is π e 7 (t) −A sin(ω1−−+θ2(t))
(7) is output. Furthermore, similarly, the output e a (t) in (d) is expressed as e e (j) −A sin(ωt −7r+02 (
j)) (8) is output.

Then, the phase divided output signal e5(t) is sent to the phase comparator 3.
, the same < e s (i) is applied to the phase comparator 4, the same < e s (i)
87 (t) is given to the phase comparator 5 with the same < e a (
t) are respectively supplied to the phase comparator 6.

Therefore, in the phase comparator 3, the phase divided output signal e + (
Phase comparison is performed by multiplying j) and 85 (t),
e 9 (t) is output as the phase comparison output signal. This e 9 (t) is expressed as e g (j) = [5in(2ω) by 10I(i
) 102 (t))-5in(θ1(t)-02([)
)] becomes ■.

Furthermore, in the phase comparator 4, the phase division output signal e 2 ((
) and e s (t) are multiplied to perform a phase comparison,
e+o(t) is output as the phase comparison output signal. This e+o(j) becomes -5in(01(j)-02(t))1@.

Furthermore, in the phase comparator 5, the phase division output signal e 3 (t
) and 87 (i) are multiplied to perform a phase comparison, and e t+ (j) is output as the phase comparison output signal. This eu(t) is 611 (t) =-ai [5in(2(c)t-7
t+81(j)+/72(j))-5in(θ1(t
)-02(t))] (11).

Furthermore, the phase comparator 6 divides the phase divided output signal e a ((
) and e e (j) are multiplied to perform a phase comparison,
e+2(t) is output as the phase comparison output signal. This e+2(t) is 15in(0+(t)-02(t) month (12)
becomes.

Then, each phase comparison output signal e 9 (t) ~
e+2(t) is supplied to the next-stage adder circuit 8, where addition is performed. The output signal et3(t) of the adder circuit 8 is 01=
02, e 13 (t) −0(13).

Also, when θ1≠02, e+3(t) is −−2A2
Sin(θ1(t)−〇2(t)) (14), which is output as a positive or negative error voltage.

Since θ1(t) and θ2(t) have relatively small values, e+
3(t) is an(t)'F-2A2 (θ1(t) -02(t
)) (15), which is supplied to vcoio as an error voltage via the loop filter 9.

Further, the output signal of this vcoio is outputted from the output terminal 11, and is also supplied to the phase division circuit 7 as described above.

As described above, the basic operation of the 7-Aze locked loop of the present invention shown in FIG. 1 is the same as that of the conventional PLL, and the operation is performed correctly.

However, in reality, it is difficult to realize this in the phase division circuit 7 in terms of the transfer function in polyphase division of analog signals.
Therefore, a multiphase output of digital signals is obtained.

First, regarding the phase division circuit 2, phase division is performed by a circuit shown in FIG. 2 as a specific example. That is, input terminal 1 in FIG. 1 corresponds to terminal 21 in FIG.
Furthermore, the phase-divided output signal eI(j) is connected to the terminal 27.
, the same < e 2 (t) is at terminal 28, the same < e
3 (t) is output to the terminal 29, and the same < 64 (t) is output to the terminal 30.

In FIG. 2, 22 is a π/2 phase shift circuit for shifting the input signal by π/2 and outputting the phase-shifted signal. From the figure, e 2 (t) output to terminal 28 is e + (t) and e 3
(t) in an adder circuit 23. Also, at(j) output to the terminal 30 is e 3 (
It is obtained by subtracting 8 + (t) from t) using the tube reduction circuit 25. Further, the resistors 24 and 26 reduce the signal level to 1/r.
It is provided to lower it to T.

Next, regarding the phase division circuit 7, as a specific example, the third
This will be explained using the circuit shown in the figure. That is, V in FIG.
The output signal of ColG is supplied to terminal 31 in FIG.

In Figure 3, a 172 frequency divider 32.33.3 is used as a divider.
EX-OR gate 34.36°31 is used. Therefore, the multiphase signals output to the output terminals 38, 39, 40° 41 are as follows.

First, at the terminal 38, a signal whose frequency is divided to 1/4 of the input signal is output. This signal corresponds to e5(t).

Next, at the terminal 39, a signal whose phase is shifted by π/4 with respect to e5(t) is output. This signal corresponds to e s (t).

Next, at the terminal 40, a signal whose phase is shifted by π/4 with respect to ea(t) is output. This signal corresponds to e 7 ([).

Further, at the terminal 41, a signal whose phase is shifted by π/4 with respect to a7(t) is output. This signal corresponds to e a (i).

That is, e5(t) is applied to terminal 38, and ea is applied to terminal 39.
(t), e 7 (t) is output to the terminal 40, and e e (D is output to the terminal 41).

Next, explanation will be given with reference to FIGS. 1, 2, and 3, and FIG. 4 showing signal waveforms at each part thereof.

In Figure 4, e + (j) is changed to (^), e 2
(t) to (B) I, , e 3 (j) to (C),
e 4 (D is shown in (D) respectively. Also, VCol
o's output signal e o (j) to (E), its e o
(t) divided by 172 signal e+t(t) to (F), e
5 (t) to (G), output signal e F (t) of EX-OR gate 34 to (H), e e (t) to (1), e 7 (t) to (J) , e s (t) is (to)
are shown respectively.

Therefore, the multiplication output of e + (t) and 85(i) is e
9(t) to (L), e 2 (t) and e e (
The multiplication output of t) is e 10(t) to (H), e
The multiplication output of 3 (t) and 87 (t) is e u (t)
The multiplication output of e4(j) and e e (t) is shown in (0) as e+2(t). Therefore, e
9(t) and e+o(j) and (3n (t) and eIt(t
) as the addition output of eo(t) becomes (P).

In addition, in this FIG. 4, it is shown as θ1-02.

Thus, using an analog multiplying phase comparator, when the signal fed to this phase comparator is fed as a digital signal to one or both inputs, there is an error signal frequency; It is obtained as the input signal frequency is multiplied.

In the embodiment of the present invention, by combining four phases,
The input signal frequency is multiplied by 8 and output as an error signal.

Next, the basic operation of the phased loop of the present invention will be explained.

The configurations of Figures 1, 2, and 3 are equivalent to Figures 5 and 6.
It will look like the picture.

That is, in FIG. 5, the signal supplied to the input terminal 51 is branched into four parts and sent to phase comparators 52, 53, 54, 5.
5 respectively.

On the other hand, the output signal of VC058 is branched into four parts and supplied to phase comparators 52, 53, 54, and 55 via 174 frequency dividers 59, 60, 61, and 62, respectively.

Then, each phase comparator performs phase comparison by multiplication, and the phase comparison output signal is supplied to the next stage adding circuit 58 for addition. Further, the output signal of the adder circuit 56 is passed through a loop filter 57 to VC05 as an error voltage.
Supplied to B. Further, the output signal of this VC058 is outputted from the output terminal 63, and is branched into four as described above and supplied to the 174 frequency dividers 59, 60, 61, and 62.

Further, in FIG. 6, the basic operation of the PLL is as follows.

The phase of the signal supplied to the input terminal 64 is 01 (s), the conversion gain of the phase comparator 65 (combined phase comparator 3.4.5°6 in FIG. 1) is Kc, and the transfer function of the loop filter 66 is F(S) and the gain of VCO67 is KO/S.

If the gain of the 174 frequency divider 68 is Kd and the phase of the output of the VCO 67 is Oo (S), it becomes -θo (S) (16), and therefore. This equation (17) is exactly the same as the conventional frequency multiplication PLL. In one embodiment of the present invention, KC is multiplied by 4, Kd is multiplied by 174, and the loop gain of the -circuit is the same as that of a conventional PLL composed of a phase comparator, a loop filter, and a VCo.

As an embodiment of the present invention, the error signal multiplication method is shown above by 8, but if this embodiment is developed, 16 multiplication, 32 multiplication, 64 multiplication, etc. can be easily applied. I can do it. In addition, in the present invention, if the comparison signal from the input signal and vCO is a square wave (duty 50%), θ1−θ
2, the error signal becomes DC. This can greatly improve the problem of angle modulation caused by error signals.

(Effect of the invention) As described above, the phase conflict locked loop of the present invention has the following effects:
By frequency-multiplying the AC component of the phase-compared error signal without impairing the basic properties of the PLL, the voltage level of the AC component of the error signal becomes smaller. , the time constant of the loop filter can be made small, thereby widening the loop band and making it possible to reduce jitter. In particular, the phase comparator and vCO
A conventional frequency multiplier constructed using a frequency divider between P
Regarding the jitter problem of vCO, which tends to be a problem in LL, since the AC component of the error signal is frequency-multiplied compared to the conventional method, the ripple component in the error signal is reduced.
Accordingly, the loop band of the PLL can be widened. (
This is because the cutoff frequency of the loop filter can be increased because the ripple component is reduced.) Similarly, the problem of the vCO frequency being angularly modulated by the alternating current component (ripple component) of the error signal can be improved by the amount of multiplication (of the error signal) compared to the conventional method if the loop band is taken as a reference.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of an embodiment of the phase-O tract loop according to the present invention, FIG. 2 is a diagram showing a specific circuit example of the phase division circuit 2 in FIG. 1, and FIG. A diagram showing a specific circuit example of the phase division circuit 7 in FIG. 1, FIG. 4 is a signal waveform diagram of each part in FIG. 1, and FIGS.
FIG. 4 is a diagram showing an equivalent circuit of the circuit configuration shown in FIGS. 1, 51.64... Input terminal, 2, 7... Phase division circuit, 3, 4.5.6.52.53.54.55.6
5... Phase comparator, 8, 23.56... Addition circuit, 9, 57.66... Loop filter (LF), 10,
58.67... Voltage controlled oscillator (VCO), 11, 6
3.69...output terminal, 22...π/2 phase shift circuit,
25... Arithmetic circuit, 24.26... Resistor, 21, 2
7.28.29.3G, 31.38.39.40.4
1...Terminal, 32.33.35...1/2 frequency divider,
34, 36.37・EX-OR gate, 59, 6G,
61.62.68...174 frequency divider.

Claims (1)

[Claims] An input signal is supplied to a phase comparator, an output signal of a voltage controlled oscillator is supplied to the phase comparator to perform phase comparison with the input signal, and an error signal is output from the phase comparator. A first plurality of phase output signals are obtained by dividing the input signal into a plurality of phases equally spaced within a range of 2π in a phase-locked loop which converts the error voltage into an error voltage through a loop filter and supplies the error voltage to the voltage controlled oscillator. is supplied to each of the divided number of phase comparators, and an output signal of the voltage controlled oscillator whose phase is shifted by π/2 from the first plurality of phase output signals corresponds to each of the first plurality of phase output signals. and the second plurality of phase output signals divided into a plurality of phases at equal intervals within a range of 2π are sent to each of the phase comparators to which the phase output signals corresponding to the first plurality of phase output signals are supplied. respectively, and each of the phase comparators performs a phase comparison between the first plurality of phase output signals and the second plurality of phase output signals, and a plurality of phase comparisons output from each of the phase comparators. A phase-locked loop characterized in that an error signal obtained by adding output signals is converted into an error voltage via a loop filter and supplied to the voltage controlled oscillator.