JPH1032486A - Fraction frequency divider and pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit capable of making the suppression of spurious noise and the enhancement of the lock-up speed compatible. SOLUTION: A phase shift circuit 27 generates plural phase shift signals FF whose phase is shifted respectively at a fixed angle at the same frequency as input signals fVCO based on the input signals fVCO. A selection circuit 28 successively selects the plural phase shift signals FF one by one based on selection signals S and outputs them. A frequency divider 29 frequencydivides the output signals X of the selection circuit 28 by the frequency division ratio of a prescribed integer. A selection signal generation circuit 32 generates the selection signals S based on the frequency division signals Pout of the frequency divider 29 and outputs them to the selection circuit 28. A counter circuit 35 outputs the count-up signals as fractional frequency division signals fp at the time of counting the prescribed number of the frequency division signals Pout of the frequency divider 29.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL which operates to match an output signal frequency to a set frequency.
The present invention relates to a comparison frequency divider used in a circuit.

In recent years, PLL circuits have been used in mobile communication devices such as mobile phones and mobile phones. Such PL
In the L circuit, it is necessary to quickly switch the output signal frequency to a desired frequency in order to improve the convenience of the mobile communication device. Therefore, it is necessary to increase the lock-up speed of the PLL circuit.

[0003]

2. Description of the Related Art FIG. 6 shows an example of a conventional PLL circuit. The oscillator 1 outputs a reference clock signal CK having a natural frequency based on the oscillation of the crystal oscillator to the reference frequency divider 2. The reference frequency divider 2 is configured by a counter circuit, divides the frequency of the reference clock signal CK based on the frequency division ratio set by the shift register 3, and outputs the reference signal fr to the phase comparator 4.

[0006] A comparison signal fp is output from the comparison frequency divider 5 to the phase comparator 4. Then, the phase comparator 4 outputs pulse signals ΦR and ΦP corresponding to the frequency difference and the phase difference between the reference signal fr and the comparison signal fp to the charge pump 6.

[0005] The charge pump 6 outputs an output signal SCP to a low-pass filter (hereinafter referred to as LPF) 7 based on the pulse signals ΦR and ΦP output from the phase comparator 4.

The output signal SCP includes a direct current component including a pulse component, and the direct current component rises and falls with the frequency fluctuation of the pulse signals ΦR and ΦP. It changes based on the phase difference.

The LPF 7 smoothes the output signal SCP of the charge pump 6 and removes the high-frequency component from the output signal SCP.
The LPF is output to a voltage controlled oscillator (hereinafter referred to as VCO) 8.

The VCO 8 outputs an output signal fvco having a frequency corresponding to the voltage value of the output signal SLPF of the LPF 7 to an external circuit and to the comparison frequency divider 5. The comparison frequency divider 5 is of a pulse swallow type, and includes a prescaler 9, a main counter 10, a swallow counter 11, and a control circuit 12.

The output signal fvco of the VCO 8 is input to the prescaler 9 which divides the frequency of the input signal fvco by M or M + 1 and outputs the output signal Pout to the main counter 10 and the swallow counter 11. Output.

The swallow counter 11 frequency-divides the output signal Pout of the prescaler 9 by A and outputs the output signal to the control circuit 12. The control circuit 12 outputs, for example, an L-level module control signal MD to the prescaler 9 based on the frequency-divided signal of the swallow counter 11, and the prescaler 9 converts the input signal fvco to M based on the module control signal MD. Divided output signal Pout
Is output.

While the swallow counter 11 is counting A pulses, the control circuit 12 outputs an H-level module control signal MD, for example, and the prescaler 9 outputs an input based on the module control signal MD. An output signal Pout obtained by dividing the signal fvco by M + 1 is output.

The frequency division ratio of the main counter 10 is set by the shift register 3 and the output signal Pout of the prescaler 9 is frequency-divided by N, and the comparison signal f is sent to the phase comparator 4.
Output as p. The frequency-divided signal of the main counter 10 is output to the control circuit 12, and the control circuit 12 outputs a start signal to the swallow counter 11 every time the main counter 10 divides the input signal Pout by N.

Therefore, in the PLL circuit, the swallow counter 11 operates every time the main counter 10 divides the output signal Pout of the prescaler 9 by N, and the prescaler 9
Is counted.

In the above PLL circuit, the VCO
In order to improve the lock-up speed of the output signal fvco of No. 8, a prescaler 9 capable of setting a fractional frequency division ratio is used.

FIG. 7 shows an example of the prescaler 9.
A plurality of accumulators 13a to 13d connected in series
In the first stage, the fraction value data FD is input, and the accumulators 13a to 13d receive the reference signal fr.

The overflow signal OVF output from each of the accumulators 13a to 13d is
Directly or via a digital delay element.

When an overflow occurs, the accumulator 13a performs an operation of increasing the frequency division ratio by one in its reference cycle, and the accumulator 13b in the second stage increases the frequency division ratio by one in response to the overflow signal. 1 is performed.

The accumulator 13c at the third stage supplies +1 for the overflow signal and-for the next reference cycle.
2, then +1 at the next stage, and the fourth stage is +1 at the overflow signal, then -3, then +3, and then -1 at the next stage.
Perform the operation of

The full adder 14 receiving these signals outputs the sum of the change in the dividing ratio and the integer value data ID to the variable divider 15 as divided data. If such a prescaler 9 is set to operate at a frequency division ratio M and a frequency division of M + 3/8, for example, it operates as shown in FIG. By doing so, an M + 3/8 frequency division operation is equivalently performed.

By using such a prescaler 9, it is possible to increase the reference frequency and reduce the time constant of the LPF 7, thereby increasing the lock-up speed of the output signal frequency fvco of the VCO 8, and The output signal frequency fvco can be changed in small steps.

[0021]

However, in the PLL circuit having the prescaler 9 as described above, since the fractional frequency division operation is performed equivalently, the frequency division ratio of the prescaler 9 is between M and M + 1. , And this change is repeated every eight reference cycles.

Then, the output signal Pout of the prescaler 9 is output.
Contains a high-frequency component.
Is modulated on the output signal frequency fvco, and spurious noise is generated on the output signal frequency fvco. The spurious noise deteriorates, for example, the reception performance of a communication device equipped with the PLL circuit.

Such spurious noise is generated by the LPF 7
However, if the time constant of the LPF 7 is increased, the lock-up speed of the output signal frequency fvco of the VCO 8 decreases.

Therefore, it has been difficult to achieve both suppression of spurious noise and improvement of lock-up speed. An object of the present invention is to provide a PLL circuit that can achieve both suppression of spurious noise and improvement in lock-up speed.

[0025]

FIG. 1 is a diagram for explaining the principle of claim 1. That is, the phase shift circuit 27 generates, based on the input signal fvco, a plurality of phase shift signals FF whose phases are shifted by a fixed angle at the same frequency as the input signal fvco. The selection circuit 28 sequentially selects and outputs the plurality of phase shift signals FF one by one based on the selection signal S. The divider 29 is connected to the selection circuit 28
Is divided by a predetermined integer division ratio. The selection signal generation circuit 32 generates the selection signal S based on the frequency division signal Pout of the frequency divider 29 and outputs the selection signal S to the selection circuit 28. When the counter circuit 35 counts the frequency-divided signal Pout of the frequency divider 29 by a predetermined number, it outputs the count-up signal as a frequency-divided signal fp.

According to a second aspect of the present invention, a reference frequency divider for dividing the reference clock signal to generate a reference signal, a phase comparator for comparing the phases of the reference signal and a comparison signal, and the phase comparator A charge pump that converts the output signal of the charge pump into a voltage signal, a low-pass filter that smoothes the output signal of the charge pump, a voltage-controlled oscillator that outputs a pulse signal having a frequency based on the output voltage of the low-pass filter, and the voltage-controlled oscillator. And a comparison divider that divides the frequency of the output signal and outputs the comparison signal as a comparison signal. The comparison frequency divider includes a prescaler that outputs a frequency-divided signal obtained by alternately dividing the output signal of the voltage-controlled oscillator at a different frequency-division ratio based on a module control signal, and a frequency-divided signal of the prescaler. A main counter for dividing the frequency of the prescaler, a swallow counter for dividing the divided signal of the prescaler, and a control circuit for generating the module control signal based on the divided signals of the main counter and the swallow counter It is composed of A pre-scaler, based on an output signal of the voltage-controlled oscillator, a phase shift circuit that generates a plurality of phase-shifted signals, each of which has a phase shifted by a fixed angle at the same frequency as the output signal; A selection circuit that sequentially selects and outputs signals one by one based on a selection signal, a frequency divider that divides an output signal of the selection circuit by a predetermined integer division ratio, and a frequency division of the frequency divider A selection signal generation circuit that generates the selection signal based on a signal and outputs the selection signal to the selection circuit, and when a predetermined number of frequency-divided signals of the frequency divider are counted,
The count-up signal is output as a fractional frequency-divided signal, and the fractional frequency-divided signal is output to the selection circuit as a module control signal, so that the selection of the phase shift signal by the selection circuit is stopped. And a counter circuit.

According to a third aspect of the present invention, the phase shift circuit receives the output signal of the voltage controlled oscillator as a clock signal and generates a plurality of phase shift signals in which the phase of the clock signal is shifted at equal intervals. The selection circuit is configured to sequentially select and output the phase shift signals one by one in the order of their phases based on the selection signal.

According to claim 4, the phase shift circuit includes:
The output signal of the voltage controlled oscillator is input by multiplying the frequency by a frequency multiplier, and the multiplication number of the frequency multiplier, the phase shift angle by the phase shift circuit, and the fractional frequency division ratio setting counter circuit Based on the count number of
The fractional division ratio can be set.

(Function) In the first aspect, when a plurality of phase shift signals output from the phase shift circuit are sequentially selected by the selection circuit and divided by the frequency divider, the divided signal of the frequency divider is divided. Is a fractional frequency-divided signal. When the fraction frequency-divided signal is counted by a counter circuit by a predetermined number, the count-up signal becomes a predetermined fraction-divided signal.

According to the present invention, the prescaler performs a fractional frequency division operation, and the output signal of the prescaler is used to count up the swallow counter, the main counter, and the fractional frequency division ratio setting counter circuit. The operation is switched between a fractional frequency dividing operation and an integer fractional operation based on the operation.

According to the third aspect, the output signal of the voltage controlled oscillator is converted into a phase shift signal whose phase is shifted at equal intervals by a phase shift flip-flop circuit, and the phase shift signal is sequentially converted by the selection circuit in the order of the phase. When the output signal of the selection circuit is frequency-divided by the frequency divider, the frequency division ratio of the frequency divider becomes a fraction.

According to a fourth aspect of the present invention, the multiplication number of the frequency multiplier is:
The fractional frequency division ratio is set by the phase shift angle of the phase shift circuit and the count number of the fractional frequency division ratio setting counter.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 2 shows a first embodiment of the present invention. The same components as those of the conventional example,
The description is given with the same reference numerals.

The comparative frequency divider 21 of this embodiment includes a frequency multiplier 22, a fractional frequency dividing prescaler 23 capable of performing frequency dividing at a fractional frequency dividing ratio of an integral multiple of 1/4, A main counter 10 and a swallow counter 11 of the same configuration, a fractional frequency division ratio setting counter 24 for performing, for example, a 3 frequency division operation by a 2-bit binary counter,
It comprises first and second control circuits 25 and 26.

The first and second control circuits 25 and 26 have the same configuration as the control circuit 12 of the conventional example. That is, the first control circuit 25 controls the swallow counter 11
And outputs an L-level module control signal MD1 to the prescaler 23 based on the frequency-divided signal.

While the swallow counter 11 is counting A pulses, the first control circuit 25 outputs the H-level module control signal MD1 to the prescaler 2.
Output to 3.

The second control circuit 26 supplies an L-level module control signal M to the prescaler 23 based on a count-up signal of the fractional frequency division ratio setting counter 24.
D2 is output.

The fraction dividing ratio setting counter 24
Is counting three pulses, the second control circuit 26 outputs the H-level module control signal MD2 to the prescaler 23. The configuration other than the comparison frequency divider 21 is the same as that of the conventional example.

The frequency multiplier 22 outputs an output signal 2f obtained by doubling the frequency of the output signal fvco of the VCO 8.
vco is output to the fractional frequency dividing prescaler 23. The specific configuration of the fractional frequency dividing prescaler 23 will be described with reference to FIG. The input signal 2fvco input from the frequency multiplier 22 is input to the flip-flop circuit 27 as a clock signal CK.

The flip-flop circuit 27 outputs the output signal FF obtained by shifting the phase of the clock signal CK by 90 degrees.
0, FF90, FF180, and FF270 are output from a known (π / 2) shift flip-flop circuit.
The output signals FF0, FF90, FF180, FF27
0 is output to the multiplexer 28.

The multiplexer 28 outputs a selection signal S
1, FF2, input signals FF0, FF90, FF
180, FF270, and output signal X
Output as

The output signal of the multiplexer 28 is output to the variable frequency divider 29. The variable frequency divider 29 includes a flip-flop circuit 31a to 31f and an OR circuit 30.
a and 30b. When the module control signal MD1 goes high, the OR circuit irrespective of the output signals of the flip-flop circuits 31d to 31f.
The output signal OR1 of the circuit 30a is fixed at the H level,
An operation of dividing the input signal X by four is performed.

When the module control signal MD1 goes low, the OR logic of the output signals of the flip-flop circuits 31d to 31f is output to the flip-flop circuit 31c as the output signal OR1, and the input signal X is divided by five. Is performed. Then, the output signal Pout is output from the last-stage flip-flop circuit 31f.

The module control signal MD2 is input to the OR circuit 30c. The output signals of the flip-flop circuits 31d to 31f are input to the OR circuit 30c.

Therefore, when the module control signal MD2 becomes H level, the flip-flop circuits 31d to 31d
The output signal OR of the OR circuit 30c regardless of the output signal of f
2 is fixed at the H level. When the module control signal MD2 goes low, the flip-flop circuit 31
The OR logic of the output signals d to 31f is output as the output signal OR2 from the OR circuit 30c.

The output signal OR2 of the OR circuit 30c is
As shown in FIG. 4, the output signal Pout of the variable frequency divider 29 becomes a pulse signal which becomes L level with a certain time width in synchronization with the rear end of the L level section.

The output signal OR2 of the OR circuit 30c is
The clock signal CK is input to the T flip-flop circuit 32a, and the output signal of the T flip-flop circuit 32a is input to the multiplexer 28 as the selection signal S1 and is input to the T flip-flop circuit 32b as the clock signal CK. The output signal of the T flip-flop circuit 32b is input to the multiplexer 28 as the selection signal S2.

The selection signals S1 and S2 become signals as shown in FIG. 4 based on the output signal OR2 of the OR circuit 30c. Based on the change of the selection signals S1 and S2, the multiplexer 28 Input signals FF0,
FF90, FF180, and FF270 are sequentially selected in this order and output as the output signal X.

Next, the operation of the comparison frequency divider 21 of the PLL circuit configured as described above will be described with reference to FIG. When the input signal 2fvco is input from the frequency multiplier 22 to the fractional frequency dividing prescaler 23, the output signals FF0, FF90,
The FFs 180 and 270 are output to the multiplexer 28.

The multiplexer 28 outputs the selection signals S1, S
2, the input signals FF0, FF90, FF180,
One of the FFs 270 is selected and output to the variable frequency divider 29.

When both the selection signals S1 and S2 are at the L level, the multiplexer 28 selects the input signal FF0 and outputs it as the output signal X. The output signal X of the multiplexer 28 is frequency-divided by the variable frequency divider 29 and output as the output signal Pout of the prescaler 23.

Main counter 10, Swallow counter 1
When the module control signals MD1 and MD2 are both at the L level by the counting operation of the 1 and fractional frequency division ratio setting counter 24, the output signal OR2 of the OR circuit 30c is output at the end of each cycle of the output signal Pout of the prescaler 23. Outputs a pulse signal that is at the L level for a certain period of time.

The selection signals S1 and S2 rise to the H level based on the first fall of the output signal OR2 of the OR circuit 30c. Then, the output signal X of the multiplexer 28 is determined based on the first fall of the output signal OR2.
Switching is performed from FF0 to FF90. .

As a result, since the FF0 is switched to the FF90 in the middle of the M frequency division operation of the variable frequency divider 29, the output signal Pout of the prescaler 23 is obtained by dividing the input signal 2fvco by M + 0.25.

Next, the output signal Pou of the prescaler 23 is output.
In the second cycle of t, the output signal OR of the OR circuit 30c is output.
When 2 falls to the L level, the selection signal S1 goes to the L level. Then, the output signal X of the multiplexer 28 becomes
Switching from FF90 to FF180 is performed.

As a result, since the FF 90 is switched to the FF 180 during the M frequency dividing operation of the variable frequency dividing section 29,
In the second cycle of the output signal Pout of the prescaler 23, the input signal 2fvco is further divided by M + 0.25.

Next, the output signal Pou of the prescaler 23
In the third cycle of t, the output signal OR of the OR circuit 30c is output.
When 2 falls to the L level, the selection signal S1 goes to the H level and the selection signal S2 goes to the L level. Then, the output signal X of the multiplexer 28 changes from FF180 to FF2.
70.

As a result, since the FF 180 is switched to the FF 270 in the middle of the M frequency dividing operation of the variable frequency dividing section 29, the input signal 2fvco is further frequency-divided by M + 0.25 in the third cycle of the output signal Pout of the prescaler 23. Will be.

When the output signal Pout of three cycles is input to the fractional frequency dividing ratio setting counter 24, the module is supplied with a count-up signal output from the fractional frequency dividing ratio setting counter 24 to the second control circuit 26. Control signal MD2
Becomes H level. By such an operation, the count-up signal of the fractional-frequency dividing prescaler 23 becomes the input signal 2f
This is a frequency-divided signal obtained by dividing vco by M + 0.75.

When the module control signal MD2 becomes H level, the output signal OR2 of the OR circuit 30c is fixed at H level, so that the selection signals S1 and S2 stop changing.
The output signal X of the multiplexer 28 is fixed to the FF 270. Therefore, the output signal Pout of the prescaler 23
Is obtained by dividing the input signal 2fvco by M.

The output signal P of such a prescaler 23
When the main counter 10, the swallow counter 11, and the fractional frequency dividing ratio setting counter 24 perform a frequency dividing operation based on the output frequency, the frequency dividing ratio of the comparative frequency divider 21 becomes MN + A + 0.
75.

With the comparative frequency divider 21 configured as described above, the following operation and effect can be obtained. (A) Since the output signal frequency fvco of the VCO 8 can be fractionally divided, the usable output signal frequency fvco can be increased while raising the reference frequency to improve the lock-up speed.
Can be increased. (B) The prescaler 23 converts the input signal 2fvco into M +
Since the output signal Pout divided by 0.25 and the output signal Pout divided by M are continuously output for a predetermined time, spurious noise generated in the output signal fvco can be reduced. (C) Since spurious components occurring in the output signal frequency fvco can be reduced, CN characteristics of a communication device using this PLL circuit can be improved. (Second Embodiment) FIG. 5 shows a second embodiment of the present invention. This embodiment is different from the first embodiment in that flip-flop circuits 33a, 33
3b is added.

That is, the flip-flop circuit 32
a is output to the flip-flop circuit 33a.
And the output signal of the flip-flop circuit 32b is input to the flip-flop circuit 33b as data D.

The flip-flop circuits 33a and 33b
, The output signal X of the multiplexer 28 is input as a clock signal G, and its flip-flop circuit 33
The output signals Q of a and 33b are input to the multiplexer 28 as the selection signals S1 and S2.

With such a configuration, the multiplexer 2
8. Spike noise in the output signal X of the multiplexer 28 due to operation delay of the flip-flop circuits 32a and 32b can be prevented. As a result, it is advantageous to increase the frequency of the input / output signal of the prescaler 23.

In the above embodiment, the output signal frequency fvco of the VCO 8 is doubled so that the flip-flop circuit 27
, And the flip-flop circuit 27 shifts the phase by 90 degrees, and the fractional frequency division ratio setting counter 24 divides the output signal Pout of the prescaler 23 by three.
Although the M + 0.75 frequency dividing operation is enabled, another fractional frequency dividing ratio can be set by changing the above setting.

[0067]

As described in detail above, the present invention can provide a PLL circuit that can achieve both suppression of spurious noise and improvement in lock-up speed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a first embodiment.

FIG. 3 is a block diagram illustrating a fractional frequency dividing prescaler according to the first embodiment.

FIG. 4 is a timing waveform chart showing an operation of the first embodiment.

FIG. 5 is a block diagram showing a second embodiment.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a block diagram showing a fractional frequency dividing prescaler of a conventional example.

FIG. 8 is a timing waveform chart showing an operation of the fractional frequency dividing prescaler of the conventional example.

[Explanation of symbols]

 27 phase difference shift circuit 28 selection circuit 29 frequency divider 32 selection signal generation circuit 35 counter circuit fvco input signal FF phase shift signal S selection signal X selection output signal Pout frequency division signal fp fraction frequency division signal

Claims (4)

[Claims] 1. A phase shift circuit for generating a plurality of phase shift signals whose phases are shifted by a fixed angle at the same frequency as the input signal based on the input signal, and a selection signal for selecting the plurality of phase shift signals. A selection circuit for sequentially selecting and outputting one by one based on a frequency divider, a frequency divider for dividing an output signal of the selection circuit by a predetermined integer division ratio, and a frequency division signal of the frequency divider. A selection signal generation circuit that generates the selection signal and outputs it to the selection circuit; and a counter circuit that outputs a count-up signal as a fractional frequency-divided signal when a predetermined number of frequency-divided signals of the frequency divider are counted. A fractional frequency divider characterized by being constituted. 2. A reference frequency divider that divides the reference clock signal to generate a reference signal, a phase comparator that compares the phases of the reference signal and a comparison signal, and an output signal of the phase comparator. To a voltage signal; a low-pass filter for smoothing an output signal of the charge pump; a voltage-controlled oscillator for outputting a pulse signal having a frequency based on an output voltage of the low-pass filter; and an output signal of the voltage-controlled oscillator. And a comparison frequency divider that divides the output signal of the voltage-controlled oscillator, based on a module control signal. A prescaler that outputs a frequency-divided signal alternately divided by a frequency division ratio; and a main counter that divides the frequency-divided signal of the prescaler to generate the comparison signal. A swallow counter for dividing the divided signal of the prescaler; and a control circuit for generating the module control signal based on the divided signals of the main counter and the swallow counter, wherein the prescaler includes the voltage control. A phase shift circuit that generates a plurality of phase shift signals each having a phase shifted at a fixed angle at the same frequency as the output signal based on the output signal of the oscillator; and A selection circuit for sequentially selecting and outputting one by one; a frequency divider for dividing an output signal of the selection circuit by a predetermined integer division ratio; and a selection signal based on the frequency division signal of the frequency divider And a selection signal generation circuit for generating the selected signal and outputting the same to the selection circuit. And a fractional frequency division ratio setting counter circuit for outputting the fractional frequency division signal as a module control signal to the selection circuit and stopping the selection of the phase shift signal by the selection circuit. Features PLL circuit. 3. The phase shift circuit comprises a phase shift flip-flop circuit which receives an output signal of a voltage controlled oscillator as a clock signal and generates a plurality of phase shift signals in which the phase of the clock signal is shifted at equal intervals. And
3. The PLL circuit according to claim 2, wherein the selection circuit sequentially selects and outputs the phase shift signals one by one in the order of their phases based on the selection signal. 4. The phase shift circuit inputs the output signal of the voltage controlled oscillator by multiplying the frequency by a frequency multiplier, and multiplies the frequency multiplier and the phase shift angle of the phase shift circuit. 3. The PLL circuit according to claim 2, wherein the fractional frequency division ratio can be set based on the count number of the fractional frequency division ratio setting counter circuit.