JPH03273632A - Ｍｉｓ型半導体装置の製造方法 - Google Patents

Ｍｉｓ型半導体装置の製造方法

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Publication number
JPH03273632A
JPH03273632A JP2073711A JP7371190A JPH03273632A JP H03273632 A JPH03273632 A JP H03273632A JP 2073711 A JP2073711 A JP 2073711A JP 7371190 A JP7371190 A JP 7371190A JP H03273632 A JPH03273632 A JP H03273632A
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Japan
Prior art keywords
plasma
substrate
mixed gas
atmosphere
gaas
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JP2073711A
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JP2770544B2 (ja
Inventor
Akiyoshi Tamura
彰良 田村
Masatoshi Kitagawa
雅俊 北川
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2073711A priority Critical patent/JP2770544B2/ja
Publication of JPH03273632A publication Critical patent/JPH03273632A/ja
Priority to US07/970,991 priority patent/US5336361A/en
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Publication of JP2770544B2 publication Critical patent/JP2770544B2/ja
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Expired - Lifetime legal-status Critical Current

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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/314—Inorganic layers
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  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は　半導体装置の製造方法に関し　特にＧａＡｓ
　（ひ化ガリウム）を用いた金属−絶縁膜一半導体（Ｍ
ＩＳ）型素子の製造方法に関するものであも 従来の技術 ＧａＡｓを用いたＭＩＳ型素子として、現在までに様々
なものが報告されていも　絶縁膜としてｃヨＳｉｎｇ　
、　ＳｉＮ、　ＡＩＮ、　ＧａＡｓ（７）プラズマ酸化
Ｕ　　陽極酸化風まｔ、　　ＡｌＧａＡｓ等の半導体層
が報告されていも発明が解決しようとする課題 しかし　こうした従来の絶縁膜を用いたＭＩＳ型素子で
は界面準位密度が１０”ｃｍ−”ｅＶ−’以上と多く、
反転層の形成も難しかった　これＬ　　ＧａＡｓ表面に
（よ　第５図のエネルギーダイアグラムに示したよう＋
Ｑ　　Ｇａ格子位置のＡｓ、　ＡｓＧａによるドナー（
エネルギーレベル０．６５ｅＶ）と、Ａｓ格子位置のＧ
ａ、　ＧａＡＳによるアクセプター（エネルギーレベル
１．１ｅＶ）の表面準位が存在するためである。−ｊ５
．　　ＡｌＧａＡｓ等の半導体層を用いたＭＩＳ型素子
でｃｔ　　界面準位密度ＣＬ　　ＳｉのＭＯ８Ｏ８Ｏ８
Ｏ８素子化上　エネルギーギャップが最大的２ｅＶＬか
なく、バイアス電圧が大きくなるとリーク電流が増大し
　バイアス余裕度が少なかった 課題を解決するための手段 本発明は上記の課題に鑑みなされたもので、第１の方法
は窒素（Ｎ２）と水素（Ｎ２）の混合ガスを用いて、電
子サイクロトロン共鳴（ＥＣＲ）プラズマを発生させ、
そのプラズマをＧａＡｓ表面に照射した後、適当な温度
で処理するものであ瓜　また　第２の方法は　アルゴン
（Ａｒ）と水素（Ｎ２）の混合ガスを用いてＥＣＲプラ
ズマを発生させ、そのプラズマをＧａＡｓ表面に照射し
た抵　大気にさらすことなく、同一のＥＣＲプラズマ装
置を用いて、引き続いて、ＳｉＮ　（窒化ケイ素）膜を
堆積した後適当な温度で処理するものであも 作用 Ｎ２とＮ２の混合ガスを用いたＥＣＲプラズマをＧａＡ
ｓ表面に照射する第１の方法で４Ｌ　　ＧａＡｓ表面上
のＡｓ原子をＮ２ガスプラズマにより蒸発させなが転Ｎ
２ガスプラズマにより窒化させ、ＧａＮを形成させるも
のである。このＧａＮζよ　エネルギーギャップが約３
．４ｅＶと大きく、絶縁膜として十分の役目を果たしこ
うして形成したＧａＡｓ／ＧａＮの界面ζよ　プラズマ
処理によりＧａＡｓ内部に形成されるため界面準位密度
がたいへん少なし１　しかもＥＣＲプラズマは　プラズ
マ発生部と、プラズマ照射部が分離しているためプラズ
マによるダメージも大へん少なｌ、％　　この少ないプ
ラズマダメージは　後の熱処理で十分回復す一＆　　−
Ｘ　　第２の方法でＣＬ　　ＧａＡｓ表面を、ＡｒとＮ
２の混合ガスを用いたＥＣＲプラズマ処理するもので、
まず、Ｎ２プラズマにより、表面に存在する過剰Ａｓ原
子を蒸発させ、ＡｓＧａドナー準位を低減すると共に　
Ａｒプラズマにより過剰Ｇａ原子を蒸発させ、ＧａＡｓ
アクセプター準位を低減するもので、その後、引き続い
て大気なさらすことなく同−ＥＣＲプラズマ装置内で、
ＳｉＮ膜を堆積することにより、ＧａＡｓ／ＳｉＮ界面
準位密度を著しく低減させるものであ、４　　ＥＣＲプ
ラズマを用いているた歇　プラズマダメージも大へん少
なく、その後の熱処理により回復させることができるも
のであも実施例 第１図（よ　本発明の第１の実施例を示したものであも
　同図（ａ）において、　ｌはｎ型ＧａＡｓ基板でＥＣ
Ｒプラズマ装置内の基板ホルダー１０に装着されていも
　まず、Ｎ２とＮ２の混合ガス（例えば混合比はＮ２：
Ｎ２＝９：１）を流り、　　２．４５ＧＨｚマイクロ波
電源で励起してＥＣＲプラズマを発生させ、これをｎ型
ＧａＡｓ基板１に照射するものであム１１はプロセスチ
ャンバー、１２はプラズマチャンバー、１３は磁気コイ
＆　　１４はＥＣＲプラズマであ＆ｎ型ＧａＡｓ基板１
（よ　この場合、約２００℃に保たれていも　このＮ２
とＮ２の混合ガスによるＥＣＲプラズマ処理により、ｎ
型ＧａＡｓ基板ｌの表面層１１　　Ａｓ原子がＮ２プラ
ズマの作用により蒸発Ｌ　Ｎ２型プラズマにより窒化が
発生１．、　　ＧａＮの層２が形成されも　下表ζよ　
主なプラズマ条件をまとめたものであも （以下余白） よりｎ型ＧａＡｓ基板１を取り出した檄　スパッタ法を
用いて、ＷＳｉ、　ＷＳｉＮ、　ＷＮ等の高融点金属を
堆積した後、ＣＦａ１０２のドライエツチングを用いて
所定の領域を残してエツチングを行ないゲート電極３を
形成する。次に同図（ｃ）に示すように　熱ＣＶＤ法を
用いて５ｉｄｅ膜４を形成した眞Ｈｚ雰囲気中で５００
ｔ。
１５分間熱処理すも　これにより、プラズマ処理で生じ
たダメージは回復する。この熱処理温度としては４５０
〜６００℃が適当であも　次に同図（ｄ）に示すよう？
Ｑ　　ＳｉＯ２膜４をフッ酸系の液を用いて除去した眞
ＡｕＧ６からなるオーミック電極５を形成してＭＩＳ型
素子を完威すも　第２図ｃ−ｔ　　本発明の第２の実施
例を示したものであも　同図（ａ）に示すように　ｎ型
ＧａＡｓ基板１がＥＣＲプラズマ装置内の基板ホルダー
に装置されてぃも　ま工ＡｒとＮ２の混合ガス（例えば
混合比はＡｒ：Ｎ２−１＋４）を流し　２、４５ＧＨｚ
マイクロ波電源で励起してＥＣＲプラズマを発生させ、
これをｎ型ＧａＡｓ基板ｌに照射するものであも　この
間ｎ型ＧａＡｓ基板１は２００ｔに加熱されてい４　　
ＨｅプラズマによりＧａＡｓ表面に過剰に存在するＡｓ
原子が蒸発しＡｓＧａドナー準位が低減しまたＡｒプラ
ズマにより、同様にＧａＡｓ表面に過剰に存在するＧａ
原子が蒸発１．、　　ＧａＡｓアクセプター単位も低減
ＬＡＧａＡｓ表面に存在する全表面準位密度を著しく低
減させるものであん　下に示す表２は主なプラズマ条件
をまとめたものであも 次に同図（ｂ）に示すように　同一のプラズマ装置内で
、大気にさらすことなく、ＳｉＨ４とＮＨｓガスを流し
て、ｎ型ＧａＡｓ基板１の表面にＳｉＮ　６を厚さ１０
０〜３００人堆積させも　次に同図（ｃ）に示すように
ｎ型ＧａＡｓ基板１をプラズマ装置より取り出した抵ｓ
ｉＮ膜上の所定の領域にリフトオフ法を用いてＡｌから
なるゲート電極７を形成した後、Ｎ２ガス雰囲気中で５
００ｔ、　　１５分間熱処理を行なう。これにより、プ
ラズマ処理によって生じたダメージが回復すもこの熱処
理温度としては４５０〜６００℃が適当であも次に同図
（ｄ）に示すように　ＡｕＧｅからなるオーミック電極
５を形成してＭＩＳ型素子を完威すも　第３図（ａ）、
（ｂ）ｉ！　　それぞれ第１＠　および第２図で示した
ＭＩＳ型素子の高周波（ＩＭＩ（ｚ）および低周波（１
０Ｈｚ）でのＣ−Ｖ　（容量−電圧）特性を示したもの
であも　同図において縦軸ζよ　絶縁膜容量ＣＩで規格
化したものであも　同図（ａ）のサンプルＣＬ　　Ｈａ
／Ｎ２ＥＣＲプラズマ照射時間１５分間のものでＧａＮ
層は約１５０人形成されていも　同図（ｂ）のサンプル
ばＡｒ／Ｎ２Ｅ　ＣＲプラズマ照射照射時間１聞さは１
００人であも　どちらＬ　基板はｎ型ＧａＡｓｕキャリ
ア濃度は３　Ｘ　１０”ｃｍ−”であも　同図より明ら
かなように　電圧は±３ｖまで耐圧があり、反転層の形
成も認められ　蓄積領域から空乏領域の遷移も急峻であ
も　第４図（ａ）、　（ｂ）にＬ　　それぞれ　第３図
（ａ）、　（ｂ）のサンプルについて、ターマン法より
求めた界面準位密度を示す。最低界面準位密度（よどち
らも１０１１オーダーとたいへん低い値を示しており良
好な界面特性が得られていることがわかも発明の詳細 な説明したようニＮ２とＮ２の混合ガスのＥＣＲプラズ
マ処理でζＬ　　ＨｅプラズマがＡｓ原子を蒸発させな
からＮ２プラズマにより、窒化が行なわれＧａＮがＧａ
Ａｓ表面に形成さＦｌ、　　ＧａＮ／ＧａＡｓの界面（
ｉ　　ＧａＡｓ表面より内部に形成されるた取　界面準
位密度も少ない良好なＭＩＳ型素子が形成されるもので
あ７．　−大ＡｒとＮ２の混合ガスのＥＣＲプラズマ処
理でｇｇ　　ＧａＡｓ表面に存在しているＡｓＧａドナ
ー準位をＮ２ガスプラズマ力交　又　ＧａＡｓアクセプ
ター準位をＡｒガスプラズマが低減し　引き続いて形成
したＳｉＮとＧａＡｓの界面準位密度ζ戴　著しく少な
く良好なＭＩＳ型素子が形成できるものであん　なお以
上の説明でＣＬ　　ｎ型ＧａＡｓ基板について説明した
力ｔｐ型ＧａＡｓ基板につしても同様であることはいう
までもなＬ％　　また　このＭＩＳ型素子を用いたＭＩ
Ｓ型ＦＥＴについても適用できることはいうまでもな（
ｔ
【図面の簡単な説明】
明の第１と第２の実施例のＭＩＳ型素子の界面準位密度
分布を示す阻　第５図はＧａＡｓ表面のエネルギーダイ
アグラムを示す図であも １１・・・・プロセスチャンバー、１２・・・・プラズ
マチャンバー、　１・・・・ｎ型ＧａＡｓ基板　２・・
・・ＧａＮ凰６・・・・ＳｉＮ嵐

Claims (2)

    【特許請求の範囲】
  1. （１）水素と窒素の混合ガスを用いて、電子共鳴サイク
    ロトロンプラズマを発生させ、上記プラズマガス中でＧ
    ａＡｓ基板の少なくとも一主面上をさらして処理した後
    、適当な温度で熱処理する工程を含むことを特徴とする
    ＭＩＳ型半導体装置の製造方法。
  2. （２）水素とアルゴンの混合ガスを用いて、電子共鳴サ
    イクロトロンプラズマを発生させ、上記プラズマガス中
    でＧａＡｓ基板の少なくとも一主面上をさらして処理し
    た後、引き続いて大気にさらすことなくＳｉＮ膜を上記
    ＧａＡｓの一主面上に堆積した後、適当な温度で熱処理
    する工程を含むことを特徴とするＭＩＳ型半導体装置の
    製造方法。
JP2073711A 1990-03-23 1990-03-23 Ｍｉｓ型半導体装置の製造方法 Expired - Lifetime JP2770544B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2073711A JP2770544B2 (ja) 1990-03-23 1990-03-23 Ｍｉｓ型半導体装置の製造方法
US07/970,991 US5336361A (en) 1990-03-23 1992-11-02 Method of manufacturing an MIS-type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2073711A JP2770544B2 (ja) 1990-03-23 1990-03-23 Ｍｉｓ型半導体装置の製造方法

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EP0833377A3 (en) * 1996-09-30 1999-08-18 Xerox Corporation Enhancement of hydrogenation of materials encapsulated by an oxide
JP2011103318A (ja) * 2009-11-10 2011-05-26 Univ Of Tokyo 半導体デバイス及びその製造方法

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US7154153B1 (en) 1997-07-29 2006-12-26 Micron Technology, Inc. Memory device
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US6965123B1 (en) 1997-07-29 2005-11-15 Micron Technology, Inc. Transistor with variable electron affinity gate and methods of fabrication and use
US6031263A (en) * 1997-07-29 2000-02-29 Micron Technology, Inc. DEAPROM and transistor with gallium nitride or gallium aluminum nitride gate
US6297538B1 (en) 1998-03-23 2001-10-02 The University Of Delaware Metal-insulator-semiconductor field effect transistor having an oxidized aluminum nitride gate insulator formed on a gallium nitride or silicon substrate
WO2003009392A1 (fr) * 2001-07-17 2003-01-30 Kabushiki Kaisha Watanabe Shoko Dispositif a semi-conducteur et son procede de fabrication et systeme d'application de ce dispositif
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US5376223A (en) * 1992-01-09 1994-12-27 Varian Associates, Inc. Plasma etch process
EP0833377A3 (en) * 1996-09-30 1999-08-18 Xerox Corporation Enhancement of hydrogenation of materials encapsulated by an oxide
JP2011103318A (ja) * 2009-11-10 2011-05-26 Univ Of Tokyo 半導体デバイス及びその製造方法

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US5336361A (en) 1994-08-09

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