JPH03175669A - Structure of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make fine the isolation region between highly concentrated 1st and 2nd conductivity type regions by providing 1st and 2nd conductivity type diffusion layers and performing like measures thereof in such a way that the 1st conductivity type diffusion layer is formed by thermal diffusion from polycrystalline silicon and the 2nd conductivity type diffusion layer is formed through ion implantation by use of a mask material including the polycrystalline silicon. CONSTITUTION:This device is composed of: a 1st region 1 which is surrounded by a field oxide film on a 1st conductivity type semiconductor substrate; an insulating film which covers the surface of the 1st region 1 after leaving a part 4 of its surface as it is; a 1st conductivity type polycrystalline silicon 5b which is provided at the peripheral region of the 1st region including the surface 4 of the 1st region 1 that is not coated with the above insulating film; a 1st conductivity type diffusion layer which is formed on the semiconductor substrate by thermal diffusion from the 1st conductivity type polycrystalline silicon 5b; a 2nd conductivity type diffusion layer 6a which is formed on the semiconductor substrate through ion implantation by making a mask material including the preceeding polycrystalline silicon 5b in the 1st region act as a mask. For example, diffusion resistance consisting of a P-type region 3 and an N<+> type region for contact of an N-type region 2 are formed as is stated before in the N-type region 2 located in an isolation region 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor integrated circuit device, and particularly to the structure of an isolation region for a diffusion region in a semiconductor integrated circuit device.

[Conventional technology]

FIG. 3 shows a conventional method for manufacturing a diffused resistor.

FIG. 3 (a) is a schematic plan view. A P wall region 3 is formed in a region 2a of N in an isolation region la separated by a field oxide film, and a high height is formed at both ends of the P wall region 3. A high concentration P+ region 6 is formed, and a high concentration N+ region 2b is formed in an isolation region lb separated by a field oxide film.
A region 8 is formed. A contact 1- region 7 is formed in the P+ region 6 and the N1 region 8. As a result, a P-type diffused resistor is formed within the isolation region la.

A schematic process 1'llT cross-sectional view taken along the line CC" in FIG. 3(a) is shown in FIG. 3(b) to (('').

First, as shown in FIG. 3(b), a field oxide film 11 is formed in an N-type region 10 made of a silicon semiconductor substrate. After forming the oxide film 12, a P wall region 13 (corresponding to the entire P region 3 in FIG. 3 (a)) which will become a resistor is formed by implanting boron ions.

Next, as shown in FIG. 3(c), an N+ region 14 (corresponding to the N4 region 8 in FIG. 3(a)) is formed by high-concentration ion implantation of arsenic, and further, by high-concentration ion implantation of boron. The P+ area L is formed 217 (corresponding to the P''J area 6 in FIG. 3(a)).

Thereafter, as shown in FIG. 3(d), an insulating film 18 is deposited, a contact region is formed, and electrodes 19.
9b to form a P-type diffused resistor. electric ff
Reference numeral 119b is an electrode (substrate contact electrode, hereinafter abbreviated as subcontact electrode) that applies a potential to the N-type region 10.

(-Problem to be Solved by the Invention) As LSI patterns become thinner, the width of the separation region between the first conductivity type high concentration region and the second conductivity type high concentration region becomes finer, It is also necessary to reduce the width of the separation region from the surrounding area.For this reason, it is necessary to reduce the separation width between the sub-contact electrode 19b and the resistor electrode 19.

In the conventional semiconductor resistor described above, the N+ region 14 and the P'' region 17 are separated by the field oxide film 11.

Since the field oxide film 11 is usually formed by a selective oxidation method using a silicon nitride film, there is a limit to its miniaturization.

Further, as a mask material for high-concentration ion implantation to form the N1 region 14 and the P+ region 17, aluminum patterned by wet etching is usually used. Since it is necessary to take into account overetching of the aluminum foil 11, there is a limit to reducing the separation width 1 from this point of view as well.

[Means to solve the problem]

The structure of the semiconductor integrated circuit device of the present invention includes: a first region surrounded by a field oxide film on a semiconductor substrate of a first conductivity type; an insulating film covering a portion of the surface of the first region;
A first conductivity type polycrystalline silicon provided in the peripheral region including the surface not covered by the insulating film, and a first conductivity type diffusion layer formed by a thermal diffusion method from the first conductivity type polycrystalline silicon. and a second conductivity type diffusion layer formed in the first region by ion implantation using a mask material containing polycrystalline silicon as a mask.

Example] Next, the present invention will be explained with reference to the drawings.

A first embodiment of the present invention will be described with reference to FIG.

FIG. 1(a) is a schematic plan view of the diffused resistor of this example. A full P region 3 exists in an N type region 2 in an isolation region 1 separated by a field oxide film, and an oxide film removed region 4 exists near the end of the N type region 2. Oxide film removal area 4
N-type high concentration polycrystalline silicon 5b exists so as to surround it. At both ends of the entire P region 3, separation regions 1. N-type high concentration polycrystalline silicon5. A P+ region 6a is provided surrounded by N-type high concentration polycrystalline silicon 5b, and an isolation region 14
41 and N-type heavily doped polycrystalline silicon 5a, a P' region 6b is provided. A contact region 7 is provided in the N-type high concentration polycrystalline silicon 5b and the P+ regions 6a and 6b.
exists.

FIGS. 1B to 1E are schematic cross-sectional views taken along line AA' in FIG. 1A.

First, as shown in Figure 1(b), the phosphorus concentration is 1015~
After forming a field oxide film 11 of approximately 0.8 Jlm on the surface of an N-type region 10 made of a silicon semiconductor substrate of 1017 cm-3 by selective oxidation using a silicon nitride film, an oxide film 12 of 10 to 70 nm is thermally oxidized. Formed by law. Subsequently, boron ions are implanted at an acceleration energy of 10 to 70 keV and a dose of 11X1013 to IX10 "cm-" to form a P wall region 13 (corresponding to the entire P region 3 in FIG. 1(a)). Next, oxidize IB! of the oxide film removal region 4! Remove 12.

Next, as shown in FIG. 1(c), 0.4~0.0.
Deposit 5 μIn of polycrystalline silicon with sheet resistance of 10
Diffuse phosphorus so that the resistance is about ~50Ω/mouth. At this time, an N+ region 14 is formed in the N-type region 10. Next, N-type high concentration polycrystalline silicon 15.15a, 15b (
Figure 1 (a> N-type high concentration polycrystalline silicon 5.5
(corresponding to a and 5b) are formed by anisotropic dry etching.

Next, as shown in FIG. 1(d), using the aluminum 16 patterned by wet etching as a mask, boron ions were implanted at an acceleration energy of 30 to 50 keV and a dose of 5 x 1015c nl-2. P+ region 1.7.17a (Fig. 1(a)
(corresponding to P+ regions 6a and 6b) are formed. At this time, the N-type heavily doped polycrystalline silicon 15b, 15 also serves as a mask for ion implantation and defines the P+ region 17.

Next, as shown in FIG. 1(e), after forming an insulating film 18 of about 0.86 m on the entire surface, an opening is made for the contact region 7, and a structure is formed in which, for example, PtS, 1TiW, and An are laminated in order from the bottom layer. Electrodes 1919a and 19b are formed.

In this embodiment, the separation width between N+ region 14 and P+ region 17 is determined by the accuracy of N-type high concentration polycrystalline silicon 15b. N-type high concentration polycrystalline silicon 151) can be etched with high processing accuracy, and the N° region 14 and P+
The separation width from the region 17 can be reduced. In addition, as shown in this example, N-type high concentration polycrystalline silicon 15..15 is used as a mask for ion implantation to form P''l acid.
By defining the resistor length using a, it is also possible to simultaneously reduce the size of the resistor.

FIG. 2 is a schematic plan view and step-by-step sectional view of a second embodiment of the present invention. In this embodiment, P channel M, OS l
- ffP+ applied to transistors.

FIG. 2(a) is a schematic plan view of this embodiment. An oxide film removed region 4 exists near the end of the N-type region 2 separated by the field oxide film, and an N-type high Concentrated polycrystalline silicon 5b and 5c are present. Further, a P+ region 6.9 is provided, and a contact region 7 is present in the N-type heavily doped polycrystalline silicon 5b and the P+ region 60.

FIGS. 2(b) to 2(d) are schematic process-order cross-sectional views taken along line B-8' in FIG. 2(a).

First, as shown in Figure 2(b), the phosphorus concentration is 10'''
-10"c +n-' made of silicon semiconductor substrate
After forming a field oxide film 11 of approximately 0.88 m in thickness on the surface of the mold region 10 by a selective oxidation method using a silicon nitride film, a gate oxide film 20 of 20 to 50 nm in thickness is formed by an aging method. Here, channel doping of the MOS transistor is performed as necessary.

Next, after removing the gate oxide film 20 in the oxide film removal region 4, polycrystalline silicon with a thickness of 0.4 to 0.5 μm is deposited on the entire surface, and phosphorus is diffused so that the sheet resistance becomes about 20Ω7/ro. Let's do it. At this time, an N+ region 14 is formed in the N type region. Next, N-type high concentration polycrystalline silicon 15b, 15
c (corresponding to N-type high concentration polycrystalline silicon 5b and 5c in FIG. 2(a)) is formed by anisotropic dry etching.

Next, as shown in FIG. 2(C), using the aluminum 16 patterned by wet etching as a mask, an acceleration energy of 7 and an Ok e V dose of 315 were applied.
By ion implantation of BF2 of X 10 I5c rn-2, P+ regions 17b and 17c (Fig.
(corresponding to P+ region 6.9). At this time,
N-type high concentration polycrystalline silicon 15b and 15c also serve as a mask for ion implantation.

Next, as shown in FIG. 2(d), after forming an insulating film 18 of about 0.8 .mu.m over the entire surface, an opening is made in the contact region 7, and electrodes 19.19a and 19b are formed.

This embodiment has the advantage that the element size of the P-channel MO3) transistor can be reduced.

Furthermore, when this embodiment is applied to a B i CM OS integrated circuit device, by using the polycrystalline silicon of the gate electrode of the CMO3 transistor in the present invention, etching of the insulating film for forming the collector region of the bipolar transistor is possible. By simultaneously performing the etching of the gate oxide film for forming the N1 diffusion layer for the sub-conductor, there is no need to add a new process.

〔Effect of the invention〕

As explained above, in the structure of the semiconductor integrated circuit device of the present invention, it is possible to finely process the width of the separation region between the high concentration region of the first conductivity type and the high concentration region of the second conductivity type provided in the semiconductor substrate. .

This method does not use a field oxide film to separate the first conductivity type high concentration region and the second conductivity type high concentration region as in the past.
This is because the width of the separation region is determined by the etching accuracy of polycrystalline silicon, which can be microfabricated.

In the conventional isolation method using a field oxide film, it is necessary to allow for an etching margin for aluminum used as a mask material for ion implantation, so the lower limit of the isolation width is 3 μm.

On the other hand, when the structure of the present invention is used, it becomes possible to reduce the separation width to the physical limit determined by the withstand voltage between the first conductivity type high concentration region and the second conductivity type high concentration region. For example, 5v
If a withstand voltage of 7 .mu.m is to be ensured assuming operation with a power supply, the separation width can be reduced to 1.5 .mu.rn even if the alignment margin is taken into account.

As shown in the embodiments of the present invention, the present invention provides a diffusion resistance, M
Although it greatly contributes to the miniaturization of O8+- transistors, in gate array type CMO8 integrated circuit devices, the reduction in the width of the isolation region described above leads to a reduction in cell size, and has a great effect on higher integration.

[Brief explanation of drawings]

FIG. 1(a) is a schematic plan view of the first embodiment of the present invention,
1(b) to 1(e) are cross-sectional views of the first embodiment of the present invention in order of steps, FIG. 2(a) is a schematic plan view of the second embodiment of the present invention, and FIG. b) to (d) are step-by-step sectional views of the second embodiment of the present invention, FIG. 3(a) is a schematic plan view of a conventional semiconductor integrated circuit device, and FIG. 3(b) to (d) 1A and 1B are process-order sectional views of a conventional semiconductor integrated circuit device. 1.1 a, 1 b...-min N area, 2.2a, 2b-
...N type region, 3...P wall region, 4...oxide film removed region, 5.5a, 5b, 5c...N type high concentration polycrystalline silicon, 6, 6a, 6b, 9 - P+ region, 7... contact region, 8... N'' region, IO
...N-type region, 11...field oxide film, 12.
...Oxide film, 13...P wall region, 14-N+ region 1
5.15a, 15b. 15c...N-type high concentration polycrystalline silicon, 16...Aluminum, 17.17a, 17b, 17c=-P" region, 18-...Insulating film, 19', L9a, 19b...-
Electrode, 20...gate oxide film.

Claims (1)

[Claims] a first region surrounded by a field oxide film on a semiconductor substrate of a first conductivity type; an insulating film that covers a portion of the surface of the first region; and a first region that is not covered with the insulating film. A first provided in the peripheral area including the surface.
a first conductivity type polycrystalline silicon, a first conductivity type diffusion layer formed on the semiconductor substrate by a thermal diffusion method from the first conductivity type polycrystalline silicon, and a first conductivity type polycrystalline silicon in the first region; A structure of a semiconductor integrated circuit device, comprising a second conductivity type diffusion layer formed in the semiconductor substrate by ion implantation using a mask material as a mask.