JPH01238166A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01238166A JPH01238166A JP6611888A JP6611888A JPH01238166A JP H01238166 A JPH01238166 A JP H01238166A JP 6611888 A JP6611888 A JP 6611888A JP 6611888 A JP6611888 A JP 6611888A JP H01238166 A JPH01238166 A JP H01238166A
- Authority
- JP
- Japan
- Prior art keywords
- region
- base
- electrode
- emitter
- gate electrode
- Prior art date
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- Pending
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000004020 conductor Substances 0.000 claims abstract description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001962 electrophoresis Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体装置の製造方法に関し、
Ｂ ｉ ＣＭＯ３素子におけるバイポーラ型トランジス
タのベース・エミッタ間の寄生抵抗成分を、製造工程を
複雑化することなく低減することを目的とし、
一導電型の半導体基板表面に、逆導電型領域からなるベ
ース領域と、該ベース領域の端部に接続する逆導電型高
濃度領域からなるベースコンタクト領域と、前記ベース
領域内に一導電型領域からなるエミッタ領域ど、該エミ
ッタ領域および前記ベースコンタクト領域にオーミック
接触するエミッタ電極およびベース電極とを具備すると
ともに、該エミッタ電極およびベース電極との間の半導
体基板上に絶縁膜を介して形成された導電性材料層から
なるゲート電極とを具備する構成とした。[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, the objective is to reduce the parasitic resistance component between the base and emitter of a bipolar transistor in a B i CMO3 element without complicating the manufacturing process. A base region consisting of an opposite conductivity type region, a base contact region consisting of an opposite conductivity type high concentration region connected to an end of the base region, and a one conductivity type semiconductor substrate surface in the base region. An emitter region consisting of a mold region is provided with an emitter electrode and a base electrode that are in ohmic contact with the emitter region and the base contact region, and an insulating film is provided on the semiconductor substrate between the emitter electrode and the base electrode. The structure includes a gate electrode made of a conductive material layer formed thereon.
本発明は半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device.
バイポーラ素子とＣＭＯ３素子とを一個のチップ上に集
積したＢｉＣＭＯ３は、バイポーラ型トランジスタの持
つ高速性と、ＣＭＯ３素子が高集積化可能で且つ消費電
力が少ないという、両者の利点を併せ持つことから近年
注目を集めている。BiCMO3, which integrates a bipolar element and a CMO3 element on a single chip, has attracted attention in recent years because it combines the advantages of both the high speed of bipolar transistors and the high integration of CMO3 elements and low power consumption. are collecting.
第４図に示すバイポーラ型トランジスタは、抵抗値の低
いベースコンタクト部ＢＣとエミッタ領域Ｅとの間隔が
広いと、両者の間の高抵抗領域Ｒの抵抗ｒが高くなり、
これが寄生抵抗としてトランジスタ特性に悪影響を及ぼ
す。そこでこの抵抗成分を低減するために色々な工夫が
なされているが、これは必ずしも容易ではない。In the bipolar transistor shown in FIG. 4, when the distance between the base contact portion BC, which has a low resistance value, and the emitter region E is wide, the resistance r of the high resistance region R between the two becomes high.
This adversely affects transistor characteristics as a parasitic resistance. Various efforts have been made to reduce this resistance component, but this is not always easy.
しかも上記ベースコンタクト領域ＢＣおよびエミッタ領
域８表面に形成されるベース電極Ｂ゛やエミッタ電極Ｅ
” の位置、およびこれらパターンの画定は、一般に位
置合わせによって行なっている。そのため」二記高抵抗
部の長さには、位置合わせのバラツキを吸収するための
、位置合わせ余裕を見込まねばならないことから必要以
上に大きくなり、しかもその寸法は一定せず、トランジ
スタの性能向上を妨げている。Moreover, the base electrode B' and the emitter electrode E formed on the surface of the base contact region BC and the emitter region 8 are
The position of `` and the definition of these patterns are generally performed by alignment. Therefore, the length of the high resistance part mentioned in ``2'' must include alignment margin to absorb alignment variations. The size of the transistor becomes larger than necessary, and its dimensions are not constant, which hinders improvements in transistor performance.
上記問題はセルファライン（自己整合）法を用いること
ができれば、位置合わせ余裕を見込む必要もなくなり、
且つ製造工程が簡単化されるが、−個のチップ上にバイ
ポーラ型素子とＣＭＯ３素子の双方を形成する必要があ
るため、一方に対する改善手段が他方に悪影響を及ぼさ
ないようにする必要があり、実際には必ずしも容易では
ない。If the above problem could be solved using the self-alignment method, there would be no need to allow for alignment margin.
In addition, the manufacturing process is simplified, but since it is necessary to form both a bipolar element and a CMO3 element on one chip, it is necessary to ensure that improvement measures for one do not have a negative effect on the other. In reality, it's not always easy.
本発明はＢ ｉ ＣＭＯ３素子におけるバイポーラ型ト
ランジスタのベース・エミッタ間の寄生抵抗成分を、製
造工程を複雑化することなく低減することを目的とする
。An object of the present invention is to reduce the parasitic resistance component between the base and emitter of a bipolar transistor in a B i CMO3 element without complicating the manufacturing process.
本発明においては、第１図に示す如く、ＢｉＣＭＯ３に
おけるバイポーラトランジスタを、エミッタ領域４とベ
ースコンタクト部３の間の半導体基板表面に、絶縁膜５
を介して形成された導電材料層からなるゲート電極Ｇを
設けた構成とした。In the present invention, as shown in FIG.
The structure includes a gate electrode G made of a conductive material layer formed through a conductive material layer.
このゲート電極Ｇは、ＭＯＳ ＦＥＴのゲート電極と
同様に働くものである。This gate electrode G functions similarly to the gate electrode of a MOS FET.
上記ゲート電極Ｇの表面には、電掻取り出し部を除いて
絶縁膜６が形成される。そこでゲート電極Ｇおよびその
表面を被覆する絶縁膜６をマスクとして、エミッタ領域
４となるｎ″層（またはｐ゛層）とベースコンタクト領
域３となるｐ゛層（またはｎ０層）を形成できる。An insulating film 6 is formed on the surface of the gate electrode G except for the electrode scraping portion. Therefore, using the gate electrode G and the insulating film 6 covering its surface as a mask, an n'' layer (or p' layer) which will become the emitter region 4 and a p' layer (or n0 layer) which will become the base contact region 3 can be formed.
従ってエミッタ領域４およびベースコンタクト領域３は
、ゲート電極と位置整合して形成できる。Therefore, emitter region 4 and base contact region 3 can be formed in alignment with the gate electrode.
そのため本発明に係るバイポーラトランジスタでは、エ
ミッタ領域４とベースコンタクト領域３との間に、位置
合わせ誤差を吸収するための位置合わせ余裕を見込む必
要がなく、従って寄生抵抗成分が小さくなるとともに、
位置合わせによる寸法やパターンのバラツキが抑制され
る。Therefore, in the bipolar transistor according to the present invention, there is no need to provide an alignment margin between the emitter region 4 and the base contact region 3 to absorb alignment errors, and therefore, the parasitic resistance component is reduced, and
Variations in dimensions and patterns due to alignment are suppressed.
更に、上記ゲート電極Ｇに適当な電圧を印加することに
より、このゲート電極Ｇ直下部にチャネル層が形成され
るので、ベース高抵抗部の抵抗を低（できる。Furthermore, by applying an appropriate voltage to the gate electrode G, a channel layer is formed directly under the gate electrode G, so that the resistance of the high resistance portion of the base can be reduced.
また、本発明では、位置合わせ余裕を見込む必要がない
ためベース領域およびエミッタ領域とも小さくできるの
で、寄生容量が減少する。Further, in the present invention, since there is no need to allow for alignment margin, both the base region and the emitter region can be made small, thereby reducing parasitic capacitance.
以下本発明の一実施例を第２図（ａ）〜（ｆ）により説
明する。An embodiment of the present invention will be described below with reference to FIGS. 2(a) to 2(f).
第２図（ａ）に見られる如く、サブストレー■−１上に
ｎ型高濃度（ｎ゛）の埋込み層１−２．その上にｎ−層
からなるコレクタ層１−３が形成された半導体ウェーハ
上に、通常の選択酸化法によりフィールド酸化膜７を形
成して、素子領域８を画定し、この素子領域８表面にｐ
型低濃度層（ｐ−層）２′と、その表面にシリコン酸化
膜のような絶縁膜５゜を形成する。As seen in FIG. 2(a), a buried layer 1-2 of n-type high concentration (n゛) is formed on the substrate 1-1. A field oxide film 7 is formed by a normal selective oxidation method on a semiconductor wafer on which a collector layer 1-3 consisting of an n-layer is formed to define an element region 8. p
A type low concentration layer (p-layer) 2' and an insulating film 5° such as a silicon oxide film are formed on the surface thereof.
本実施例では、上記コレクタ層１−３が半導体基板また
は層１に相当する。従って本実施例ではｎ型が一導電型
、ｐ型が逆導電型となる。In this embodiment, the collector layer 1-3 corresponds to the semiconductor substrate or layer 1. Therefore, in this embodiment, the n-type is of one conductivity type, and the p-type is of the opposite conductivity type.
以下説明の便宜のため第２図（ｂ）〜（ｅ）には、サブ
ストレー）１−１．埋込み層１−２は図示しない。For convenience of explanation below, FIGS. 2(b) to (e) show sub-strata) 1-1. The buried layer 1-2 is not shown.
次いで（ｂ）に示す如く上記絶縁膜５”上に、多結晶シ
リコン層とその上にＳ ｉ Ｏｚ層を堆積し、これの不
要部を除去して、多結晶シリコン（ｐｏｌｙ Ｓｉ）か
らなるゲート電極Ｇ、およびその上面を被覆する絶縁膜
６を形成する。Next, as shown in (b), a polycrystalline silicon layer and a SiOz layer are deposited on the insulating film 5'', and unnecessary portions of this are removed to form a gate made of polycrystalline silicon (polySi). An electrode G and an insulating film 6 covering the upper surface thereof are formed.
次いで（Ｃ）に示す如く、上記絶縁膜６．ゲート電極Ｇ
と図示はしていないがレジスト膜とを併用して、イオン
注入法により砒素（Ａｓ）や燐（Ｐ）のようなｎ型不純
物を導入してｎ゛層（エミッタ領域）４を形成し、次い
でボロン（Ｂ）のようなｎ型不純物を導入してｐ°層３
°を形成する。Next, as shown in (C), the insulating film 6. Gate electrode G
Although not shown, an n-type impurity such as arsenic (As) or phosphorus (P) is introduced by ion implantation using a resist film to form an n layer (emitter region) 4. Next, an n-type impurity such as boron (B) is introduced to form the p° layer 3.
Form a °.
次いで（ｄ）に示す如く、半導体基板上全面に５ｉ０２
層を堆積し、これの不要部をリアクティブイオンエツチ
ング（ＲＩＥ）法により除去して、素子領域８の表面を
露呈させる。これによってゲート電極Ｇの側壁部に側壁
ＳｉＯ□層６°が形成され、ゲート電極Ｇの要部がすべ
て被覆される。この側壁５ｉＯｚ層６゛とゲート電極Ｇ
上面のＳｉＯ□からなる絶縁膜６は同じ材質であるので
、この両者は一体化し、ゲート電極Ｇは絶縁膜６，６゜
に埋め込まれた形となる。Next, as shown in (d), 5i02 was applied all over the semiconductor substrate.
A layer is deposited and unnecessary portions thereof are removed by reactive ion etching (RIE) to expose the surface of device region 8. As a result, a sidewall SiO□ layer 6° is formed on the sidewall portion of the gate electrode G, and the main portion of the gate electrode G is entirely covered. This sidewall 5iOz layer 6' and the gate electrode G
Since the insulating film 6 made of SiO□ on the upper surface is made of the same material, the two are integrated, and the gate electrode G is embedded in the insulating films 6, 6°.
なお上記（Ｃ）、 （ｄ）で説明した工程は次のように
変形しても良い。Note that the steps described in (C) and (d) above may be modified as follows.
即ち、（Ｃ）の工程で形成したｎ゛層４び２１層３′は
、上記側壁Ｓｉｎ、層を形成した後にイオン注入法によ
り形成しても良い。この場合には、ベースコンタクト領
域とエミッタ領域との間隔が大きくなり、その分抵抗値
が高くなるが、この工程に従えば、図には示していない
ＭＯＳ）ランジスタ部の形成と、バイポーラトランジス
タの形成とを同一工程で同時に行うことができるという
利点がある。またこの製造工程によれば、エミッタ領域
の幅を小さくできるという効果を生じる。That is, the n layer 4 and the 21 layer 3' formed in the step (C) may be formed by ion implantation after forming the side wall Sin layer. In this case, the distance between the base contact region and the emitter region becomes larger, and the resistance value increases accordingly, but if you follow this process, you will be able to form a MOS transistor (not shown) and a bipolar transistor. There is an advantage that the formation can be performed simultaneously in the same process. This manufacturing process also has the effect of reducing the width of the emitter region.
次いで（ｅ）に示す如く、素子領域８の露呈している表
面、即ち、ベースコンタクト領域３とエミッタ領域４の
表面と接触するｎ型不純物およびｎ型不純物を所定量含
有する多結晶シリコン層を堆積させ、これの不要部を選
択的に除去して、ベース電極Ｂ゛およびエミッタ電極Ｅ
゛を形成する。Next, as shown in (e), a polycrystalline silicon layer containing an n-type impurity and a predetermined amount of n-type impurity is formed in contact with the exposed surface of the element region 8, that is, the surfaces of the base contact region 3 and the emitter region 4. The base electrode B' and the emitter electrode E are formed by selectively removing unnecessary parts of the deposited parts.
form.
なお、前述のエミッタ領域であるｎ“層４は、本工程終
了後にエミッタ電極Ｅ”を拡散源とし、エミッタ電極Ｅ
°中に含まれるｎ型の不純物を拡散させて形成してもよ
い。Note that the n" layer 4, which is the emitter region mentioned above, uses the emitter electrode E" as a diffusion source after this process is completed, and the emitter electrode E"
It may also be formed by diffusing n-type impurities contained in the material.
このあと、ＰＳＧ （燐シリケートガラス）層９および
Ａｆｆｉからなる引き出し電極１０．１１を形成して、
第２図（ｆ）に示すような本発明に係るバイポーラトラ
ンジスタが完成する。After that, a PSG (phosphorus silicate glass) layer 9 and an extraction electrode 10.11 made of Affi are formed.
A bipolar transistor according to the present invention as shown in FIG. 2(f) is completed.
上記本実施例のバイポーラトランジスタは、エミッタ領
域およびベースコンタクト領域ｌ域がゲート電極に自己
整合的に形成されるので、位置合わせ誤差がなく、その
ためベースコンタクト領域とエミッタ領域との間に位置
合わせ余裕を見込む必要がなく、また位置合わせ誤差に
よる寸法のバラツキがない。従って高抵抗部の長さを短
くすることができる。In the bipolar transistor of this embodiment, the emitter region and the base contact region 1 are formed in a self-aligned manner with the gate electrode, so there is no alignment error, and therefore there is alignment margin between the base contact region and the emitter region. There is no need to take into account the difference in size, and there is no variation in dimensions due to alignment errors. Therefore, the length of the high resistance portion can be shortened.
更に、上記ゲート電極Ｇに通常のＭＯＳ）ランジスタと
同様に、ゲート電圧を印加しておくと、ゲート電極Ｇ直
下のｐ型層内にチャネルが形成されるので、導電率が高
まるという効果がある。Furthermore, if a gate voltage is applied to the gate electrode G as in a normal MOS transistor, a channel is formed in the p-type layer directly under the gate electrode G, which has the effect of increasing conductivity. .
ゲート電極Ｇは、ベース電極とは短絡してもよいが、エ
ミッタ電極と短絡すると、エミッタ・ベース間の寄生容
量が増加するので、好ましくない。Although the gate electrode G may be short-circuited with the base electrode, short-circuiting with the emitter electrode is not preferable because the parasitic capacitance between the emitter and the base increases.
なお上記一実施例ではゲート電極Ｇを絶縁膜で覆った例
を説明したが、ゲート電極Ｇは必ずしも絶縁膜で覆う必
要はない。Although the above embodiment describes an example in which the gate electrode G is covered with an insulating film, the gate electrode G does not necessarily need to be covered with an insulating film.
第３図は本発明の他の実施例を示す図であって、ベース
電極Ｂ′およびエミッタ電極Ｅ゛をＡ２で形成した例で
ある。FIG. 3 is a diagram showing another embodiment of the present invention, in which the base electrode B' and the emitter electrode E' are formed of A2.
このように本発明は、種々変形して実施し得るものであ
って、上記一実施例および他の実施例に限定されるもの
ではない。As described above, the present invention can be implemented with various modifications, and is not limited to the above embodiment and other embodiments.
以上説明した如く本発明によれば、ベース抵抗を安定に
低くすることが可能であり、また、本発明に係るバイポ
ーラトランジスタは、その各部をＣＭＯ３素子の各部を
形成する工程で同時に形成できるので、Ｂ ｉ ＣＭＯ
３として工程を増加しないで、Ｂｉｐミルトランジスタ
能を上げることができる。As explained above, according to the present invention, it is possible to stably lower the base resistance, and each part of the bipolar transistor according to the present invention can be formed simultaneously in the process of forming each part of the CMO3 element. B i CMO
3, Bip mill transistor performance can be increased without increasing the number of steps.
第１図は本発明の構成説明図、
第２図（ａ）〜（ｆ）は、本発明一実施例をその製造工
程とともに示す図、
第３図は本発明の他の実施例説明図、
第４図は従来のＢ ｉ ＣＭＯ３の問題点説明図である
。
図において、１は半導体基板または層、２はベース領域
、３はベースコンタクト領域、４はエミッタ領域、６は
絶縁膜、Ｇはゲート電極、Ｂｏはベース電極、ＢＣはベ
ースコンタクト領域、Ｅはエミッタ領域、Ｅｏはエミッ
タ電極を示す。
４： エミー／７ｎｉ戊゛
Ｂｏ二 ベース電泳
Ｅ’： Ｉミ１り’ｔＪａ
Ｇ： ７−）−’を招
７Ｉ−発σ月＾」〆ｋＴｔ、Ｏ月閏
第１図
不ネｇ、ｆｆ−τ始例ε号の源遣ゴ￥し１１：ネＴｍ第
２図FIG. 1 is an explanatory diagram of the configuration of the present invention; FIGS. 2(a) to (f) are diagrams showing one embodiment of the present invention together with its manufacturing process; FIG. 3 is an explanatory diagram of another embodiment of the present invention; FIG. 4 is an explanatory diagram of problems in the conventional B i CMO3. In the figure, 1 is a semiconductor substrate or layer, 2 is a base region, 3 is a base contact region, 4 is an emitter region, 6 is an insulating film, G is a gate electrode, Bo is a base electrode, BC is a base contact region, and E is an emitter. The region Eo indicates the emitter electrode. 4: Emmy/7ni゛Bo2 Base Electrophoresis E': Imi1ri'tJa G: 7-)-' is invited 7I-departing σ month^'' 〆kTt, O month leap 1st figure non-neg, ff -τ first example ε issue's source code 11: NeTm Figure 2
Claims (3)
導電型領域からなるベース領域（２）と該ベース領域の
端部に接続する逆導電型高濃度領域からなるベースコン
タクト領域（３）と、前記ベース領域内に一導電型領域
からなるエミッタ領域（４）と、該エミッタ領域および
前記ベースコンタクト領域にオーミック接触するエミッ
タ電極（Ｅ′）およびベース電極（Ｂ′）とを具備する
とともに、該エミッタ電極およびベース電極との間の半
導体基板上に絶縁膜を介して形成された導電性材料層か
らなるゲート電極（Ｇ）とを具備することを特徴とする
半導体装置。(1) On the surface of a semiconductor substrate or layer (1) of one conductivity type, a base region (2) consisting of a region of the opposite conductivity type and a base contact region (2) consisting of a high concentration region of the opposite conductivity type connected to the end of the base region ( 3), an emitter region (4) consisting of a region of one conductivity type in the base region, and an emitter electrode (E') and a base electrode (B') that are in ohmic contact with the emitter region and the base contact region. A semiconductor device comprising: a gate electrode (G) made of a conductive material layer formed on a semiconductor substrate between the emitter electrode and the base electrode with an insulating film interposed therebetween.
）を有し、前記エミッタ領域（４）および前記ベースコ
ンタクト領域（３）が、前記ゲート電極（Ｇ）側面の絶
縁膜（６）と、素子領域（８）を画定するフィールド酸
化膜（７）により画定されていることを特徴とする請求
項（１）記載の半導体装置。(2) An insulating film (6
), in which the emitter region (4) and the base contact region (3) define an insulating film (6) on the side surface of the gate electrode (G) and a field oxide film (7) defining an element region (8). 2. The semiconductor device according to claim 1, wherein the semiconductor device is defined by:
およびベースコンタクト領域（３）が画定されているこ
とを特徴とする請求項（１）記載の半導体装置。(3) Emitter region (4) by the gate electrode (G)
2. The semiconductor device according to claim 1, further comprising a base contact region (3) and a base contact region (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6611888A JPH01238166A (en) | 1988-03-18 | 1988-03-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6611888A JPH01238166A (en) | 1988-03-18 | 1988-03-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01238166A true JPH01238166A (en) | 1989-09-22 |
Family
ID=13306645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6611888A Pending JPH01238166A (en) | 1988-03-18 | 1988-03-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01238166A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003179067A (en) * | 2001-09-18 | 2003-06-27 | Agere Systems Guardian Corp | Bipolar junction transistor compatible with vertical replacement gate transistor |
| JP2005252158A (en) * | 2004-03-08 | 2005-09-15 | Yamaha Corp | Bipolar transistor and manufacturing method therefor |
| JP2009059785A (en) * | 2007-08-30 | 2009-03-19 | Seiko Instruments Inc | Semiconductor device |
| JP2017079260A (en) * | 2015-10-20 | 2017-04-27 | 株式会社リコー | Semiconductor device, imaging device, electronic apparatus and method for manufacturing semiconductor device |
-
1988
- 1988-03-18 JP JP6611888A patent/JPH01238166A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003179067A (en) * | 2001-09-18 | 2003-06-27 | Agere Systems Guardian Corp | Bipolar junction transistor compatible with vertical replacement gate transistor |
| JP2005252158A (en) * | 2004-03-08 | 2005-09-15 | Yamaha Corp | Bipolar transistor and manufacturing method therefor |
| JP2009059785A (en) * | 2007-08-30 | 2009-03-19 | Seiko Instruments Inc | Semiconductor device |
| JP2017079260A (en) * | 2015-10-20 | 2017-04-27 | 株式会社リコー | Semiconductor device, imaging device, electronic apparatus and method for manufacturing semiconductor device |
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