JPH01105578A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01105578A JPH01105578A JP62261591A JP26159187A JPH01105578A JP H01105578 A JPH01105578 A JP H01105578A JP 62261591 A JP62261591 A JP 62261591A JP 26159187 A JP26159187 A JP 26159187A JP H01105578 A JPH01105578 A JP H01105578A
- Authority
- JP
- Japan
- Prior art keywords
- mask
- source
- pattern
- forming
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 150000004767 nitrides Chemical class 0.000 claims abstract 4
- 238000009792 diffusion process Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法、特にＤＳＡ構造（Ｄｉ
ｆｆｕｓｉｏｎ Ｓｅｌｆ−Ａｌｉｇｎｍｅｎｔ ）
の縦形の高耐圧パワーとＭＯＳＦＥＴの微細化技術に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, particularly a DSA structure (Di
fffusion Self-Alignment)
This paper relates to vertical high-voltage power and MOSFET miniaturization technology.
ＤＳＡ構造のパワーＭＯ８ＦＥＴについては、（２）工
業調量会発行の電子材料１９８１年９月ｐ、４４〜４８
に記載されている。Regarding the power MO8FET with DSA structure, see (2) Electronic Materials, published by Japan Industrial Measures Association, September 1981, p. 44-48.
It is described in.
このＤＳ人構造は、たとえば、第７図を参照し、ドレイ
ンとなるｎ１１８ｉ基板１の表面にポリＳｉからなる絶
縁ゲート３を形成し、このゲート３をマスクにしてベー
ス（ｐ型領域）５及びソース（ｎ＋型領領域６を二重に
拡散するこ１とＫよりチャネル長を自己整合的に規定し
、ＭＯ８ＦＥＴセルの高集積化が可能となっている。In this DS structure, for example, referring to FIG. 7, an insulated gate 3 made of poly-Si is formed on the surface of an n118i substrate 1 serving as a drain, and using this gate 3 as a mask, a base (p-type region) 5 and a By doubly diffusing the source (n+ type region 6) and K, the channel length is defined in a self-aligned manner, making it possible to achieve high integration of MO8FET cells.
なお、ソース電極１０はバックゲート（ベース）、５と
短路させ、このベースの一部は高濃度のベース取出し１
層８が設け、られる。Note that the source electrode 10 is short-circuited to the back gate (base) 5, and a part of this base is connected to the high concentration base extraction 1.
A layer 8 is provided and covered.
上述したソース電極を加工する部分は、（１）ｎ”拡散
のための系トレジストパターン形成、り拡散のためのホ
トレジストバタτン形成、（３）ソース電極コンタクト
孔あけのためのホトレジストバターン形成と多くのホト
レジスト工程が必要であり、これらのマスクパターンの
位置合わせのために、セルの寸法を余裕をもたせなけれ
ばならず、これ以上の微細化のネックとなっていた。The above-mentioned source electrode processing steps include (1) formation of a resist pattern for n'' diffusion, formation of a photoresist pattern for diffusion, and (3) formation of a photoresist pattern for forming a source electrode contact hole. Many photoresist steps are required, and in order to align these mask patterns, the cell dimensions must be made with some margin, which poses a bottleneck to further miniaturization.
本発明は上記した問題点を解決するためのものであって
、その目的とするところは、ソース電極取り出し部につ
いてもセルファライン化し、さらにＭＯＳＦＥＴのセル
の微細化を図ることにある。The present invention is intended to solve the above-mentioned problems, and its purpose is to make the source electrode extraction portion also self-aligned and to further miniaturize the MOSFET cell.
本発明の前記ならびにそのはかの目的と新規な特徴は、
本明細書の記述と添付図面からあきらかくなろう。The above and further objects and novel features of the present invention are:
It will become clear from the description of this specification and the accompanying drawings.
本願忙おい【開示される発明のうち代懺的なものの概要
を簡単に説明すれば下記のとおりである。A brief summary of the most representative inventions disclosed herein is as follows.
すなわち、半導体基板の一主ＩＩ藺にポリＳｉゲートを
形成し、このゲートを用いてベース及びソースの二重拡
散層を形成する縦形ＭＯ８ＦＥＴの製造方法におい【、
上記ソース拡散は基板上に形成したＳｉ３Ｎ２（シリコ
ン窒化物）マスクによりソース他端を規定し、この８５
Ｎ４１にマスクを用いてゲート表面及びソース拡散層表
面に選択的に酸化膜を形成した後、この激化膜をマスク
にしてベース表面にベース・コンタクト用高濃度拡散層
を形成するものである。That is, in a method for manufacturing a vertical MO8FET, in which a poly-Si gate is formed on one main layer of a semiconductor substrate, and a double diffusion layer of a base and a source is formed using this gate.
For the source diffusion, the other end of the source is defined by a Si3N2 (silicon nitride) mask formed on the substrate, and this 85
After selectively forming an oxide film on the gate surface and the source diffusion layer surface using a mask for N41, a high concentration diffusion layer for base contact is formed on the base surface using this oxidized film as a mask.
上述した手段によれば、ベース・コンタクト用高濃度拡
散層形成用のマスクパターンの形成はセルファライン化
され、精度を要するパターンはＳｉ、Ｎ４ハターンのみ
であって、目合せの余裕がとれ、寸法の縮小化を実現で
きる。According to the above-mentioned means, the mask pattern for forming the high-concentration diffusion layer for the base contact is formed in a self-lined manner, and the only patterns that require precision are Si and N4 patterns, allowing for margins in alignment and size control. It is possible to achieve reduction in size.
第１図ないし第６図は本発明の一実施例を示すものであ
って、ＤＳＡ構造のパワーＭＯ８ＦＥＴの製造プロセス
を各工程で示す断面図である。1 to 6 show one embodiment of the present invention, and are cross-sectional views showing each step of the manufacturing process of a power MO8FET having a DSA structure.
以下各工程順に説明する。Each process will be explained in order below.
口） 第１図に示すように半導体基板、たとえばｎ″″
ＩＬＳｉ基板ｌを熱酸化してゲート酸化膜２を形成し、
その上にポリＳｔをデポジットしパターニングしてポリ
Ｓｉゲート３のパターンを形成する。) As shown in Figure 1, a semiconductor substrate, for example n''''
The ILSi substrate 1 is thermally oxidized to form a gate oxide film 2,
Poly-St is deposited thereon and patterned to form a poly-Si gate 3 pattern.
（２） ５ｉｌＮ４をデポジットし、次いでパターニン
グして第２図忙示すようにベースコンタクト部なのこす
ようにＳｉ、Ｎ４マスク４を形成する。(2) 5ilN4 is deposited and then patterned to form a Si,N4 mask 4 over the base contact portion as shown in FIG.
（３） 上記Ｓｉゲート３及びＳｉ、Ｎ４膜マスク４
を！スフ忙アクセプタ（たとえばＢ）及びドナ（たとえ
ば人Ｓ）を順次イオン打込み・拡散してＩＥ３図に示す
ようにベースｐａ１層５及びソースｎ＋型層６を形成す
る。なお、ペースｐＷｉ層は深く拡散することによって
底部でオーバラップさせる。(3) The above Si gate 3 and Si, N4 film mask 4
of! An acceptor (for example, B) and a donor (for example, S) are sequentially ion-implanted and diffused to form a base PA1 layer 5 and a source n+ type layer 6 as shown in Figure IE3. Note that the paste pWi layer is overlapped at the bottom by deep diffusion.
＋４１ ５ｉｌＮ４膜マスクを用いて選択酸化を行い、
第４図に示すよ５にＳｉ、Ｎ４膜の形成されズないノー
スｎ＋型層６の表面およびポリＳｉゲートの表面に酸化
膜（ＳｉＯｘ）７を厚く形成する。Perform selective oxidation using +41 5ilN4 film mask,
As shown in FIG. 4, a thick oxide film (SiOx) 7 is formed on the surface of the N+ type layer 6 where the Si and N4 films are not formed, and on the surface of the poly-Si gate.
（５１８５Ｎ４膜を熱リン酸等忙より取り除いた状態で
ＢＳＧ（ボロン・シリケート・ガラス）をデポジットし
、激化膜７をマスクに拡散することにより第５図に示す
ようにベースコンタクト用ｐ＋層８を形成する。(After removing the 5185N4 film using hot phosphoric acid, etc., deposit BSG (boron silicate glass) and diffuse the intensified film 7 as a mask to form a p+ layer 8 for base contact as shown in FIG. Form.
（６）全［ＫＰＳＧ（リン・シリケート・ガラス）９を
デポジットし、ついで、コンタクト用ホトエッチを行い
、ＡＪをスパッタし、パターニングして第６図忙示すよ
うにペースｐ＋層を短絡するソースＡＪ電極１０を形成
すること忙よりＭＯＳＦＥＴを完成する。(6) Deposit all KPSG (phosphorus silicate glass) 9, then photo-etch for contact, sputter AJ, pattern and short-circuit the paste p+ layer as shown in Figure 6 Source AJ electrode 10 and completed the MOSFET.
上記した実施例から得られた作用効果は下記のとおりで
ある。The effects obtained from the above examples are as follows.
（１１従来ペース取出しｐ＋拡散のためのマスク工程ト
、コンタクト孔あけのためのマスク工程とを別のホトレ
ジスト加工により形成するため、マスク位置合せ余裕を
必要としたが、本発明ではＳｉ、Ｎ。(11) Conventionally, the mask process for taking out the paste p+ and the mask process for forming the contact hole were formed by separate photoresist processing, so a margin for mask alignment was required, but in the present invention, Si, N.
パターンのための１回のマスク工程ですみ、位置合せの
余裕を必要としないためチップ全体の寸法を小さくする
ことかできる。Only one mask process is required for patterning, and no alignment margin is required, so the overall size of the chip can be reduced.
たとえばセル寸法を従来５μｍ程度であるのに対し本発
明では３μｍが可能となった。For example, while the cell size is conventionally about 5 μm, the present invention allows the cell size to be 3 μm.
（２： 一つのチップでセルの一数が多いことにより
、１つのセル寸法の節減からトータルの場合、たとえば
１００セルとして２００μｍの差、面積忙して２００
μｍの差ができる。(2: Due to the large number of cells in one chip, the total size of each cell is reduced, for example, for 100 cells, there is a difference of 200 μm, and the area is 200 μm.
A difference of μm can be made.
＋３１ セルファライン技術であることにより、歩留
りの向上が期待できる。+31 Since it is a self-line technology, it is expected that the yield will improve.
以上本発明者によりてなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能である。Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof.
本Ｂにおいて開示される発明のうち代表的なものにより
て得られる効果を簡単に説明すれば下記のとおりである
。A brief explanation of the effects obtained by typical inventions among the inventions disclosed in Book B is as follows.
すなわち、ＤＳＡ構造のＭＯＳＦＥＴにおいて、チャネ
ル長及びソースコンタクト部のセルファライン化ができ
、チップ寸法の大幅な縮小な央現できる。That is, in a MOSFET having a DSA structure, the channel length and source contact portion can be made self-aligned, and the chip size can be significantly reduced.
第１図乃至第６図は本発明の一実施例を示すものであっ
て、ＤＳＡ構造のＭＯＳＦＥＴの製造プロセスにおける
各工程の断面図である。
第７図はＤＳＡ構造のＭＯＳＦＥＴの一例を示す断面図
である。
第８図は第７図に等価の回路図である。
゛ ｌ・・・Ｓｉ基板１．３・・・ポリＳｉゲート、
４・・・Ｓｉ八へスク、５・・・ペースｐＪｌ、６・・
・ソースｎ”ｌ、７・・・５ｉＯｘｆｆｌ、８・・・ペ
ースコンタクトル＋層、１０・・・Ａ１電極。
第 １ 図
第 ３ 図
ｊぺ−Ｚ
第 ５ 因
第 ６ 図
０Ａ１1 to 6 show one embodiment of the present invention, and are sectional views of each step in the manufacturing process of a MOSFET having a DSA structure. FIG. 7 is a sectional view showing an example of a MOSFET having a DSA structure. FIG. 8 is a circuit diagram equivalent to FIG. 7.゛ l...Si substrate 1.3...poly-Si gate,
4...Si Hachihesuku, 5...Pace pJl, 6...
・Source n"l, 7...5iOxffl, 8...Pace contact + layer, 10...A1 electrode.
Claims (1)
基板表面にベース及びソースの二重拡散層を形成する縦
型ＭＯＳＦＥＴの製造方法であって、上記基板上に半導
体窒化膜のマスクを形成しておき、この窒化膜マスクに
よりソース拡散層の他端を規定するとともに、上記窒化
膜マスクを用いてゲート表面及びソース拡散層表面に選
択的に酸化膜を形成した後、この酸化膜をマスクにして
ベース表面にベース・コンタクト用の高濃度拡散層を形
成することを特徴とする半導体装置の製造方法。1. A method for manufacturing a vertical MOSFET in which a gate formed on one main surface of a semiconductor substrate is used to form a base and source double diffusion layer on the substrate surface, the method comprising: forming a semiconductor nitride film mask on the substrate; This nitride film mask defines the other end of the source diffusion layer, and the nitride film mask is used to selectively form an oxide film on the gate surface and the source diffusion layer surface. A method for manufacturing a semiconductor device, comprising forming a highly concentrated diffusion layer for a base contact on a base surface using a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62261591A JPH01105578A (en) | 1987-10-19 | 1987-10-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62261591A JPH01105578A (en) | 1987-10-19 | 1987-10-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01105578A true JPH01105578A (en) | 1989-04-24 |
Family
ID=17364047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62261591A Pending JPH01105578A (en) | 1987-10-19 | 1987-10-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01105578A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0769811A1 (en) * | 1995-10-19 | 1997-04-23 | Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe | Method of fabricating self aligned DMOS devices |
| EP1088750A2 (en) | 1999-09-30 | 2001-04-04 | Honda Giken Kogyo Kabushiki Kaisha | Scooter floor step structure |
| WO2011013380A1 (en) * | 2009-07-31 | 2011-02-03 | Fuji Electric Systems Co., Ltd. | Manufacturing method of semiconductor apparatus and semiconductor apparatus |
-
1987
- 1987-10-19 JP JP62261591A patent/JPH01105578A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0769811A1 (en) * | 1995-10-19 | 1997-04-23 | Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe | Method of fabricating self aligned DMOS devices |
| EP1088750A2 (en) | 1999-09-30 | 2001-04-04 | Honda Giken Kogyo Kabushiki Kaisha | Scooter floor step structure |
| WO2011013380A1 (en) * | 2009-07-31 | 2011-02-03 | Fuji Electric Systems Co., Ltd. | Manufacturing method of semiconductor apparatus and semiconductor apparatus |
| CN102484073A (en) * | 2009-07-31 | 2012-05-30 | 富士电机株式会社 | Manufacturing method of semiconductor apparatus and semiconductor apparatus |
| JP2012527114A (en) * | 2009-07-31 | 2012-11-01 | 富士電機株式会社 | Semiconductor device manufacturing method and semiconductor device |
| US9136352B2 (en) | 2009-07-31 | 2015-09-15 | Fuji Electric Co., Ltd. | Manufacturing method of semiconductor apparatus and semiconductor apparatus |
| US9312379B2 (en) | 2009-07-31 | 2016-04-12 | Fuji Electric Co., Ltd. | Manufacturing method of semiconductor apparatus and semiconductor apparatus |
| US9496370B2 (en) | 2009-07-31 | 2016-11-15 | Fuji Electric Co., Ltd. | Manufacturing method of semiconductor apparatus and semiconductor apparatus |
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