JPS61198673A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the junction capacitance by determining the space between the inactive region by the thickness of the insulation layer, thereby making the whole semiconductor device small-sized. CONSTITUTION:An N<+> buried layer 32 and a P buried region 33 are formed on a P-type silicon substrate 31, an N-type silicon layer 34 is grown thereon, and an isolation oxide film 35 is formed by patterning a nitride film. After removing the nitride film, a mask material is applied, boron ions are struck into, and heat treatment is performed, thereby making a P-type base region 37, and polysilicon 38 is deposited. Then, an N-type impurity is duffused to form polysilicon 39 and polysilicon 40, and oxidation is performed to form thick oxide films 41 and 42 on the polysilicons 39 and 40 and a thin oxide film on the base region 37. After removing the oxide film on the base region 37, a BSG film is deposited and removed by etching, thereby leaving BSG films 44 and 45 only on the side walls of the oxide film 41. Polysilicon 46 is deposited, boron ions are implanted and diffused, and etching-back is performed. After patterning this, thermal oxidation is performed, and finally emitter electrode metal 52, base electrode metal 53 and collector electrode metal 54 are vacuum deposited, respectively.

Description

[Detailed description of the invention]

[Industrial Field of Application 1] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device that is intended to reduce the size and improve the performance of a semiconductor device having at least a control electrode region and a main electrode region. [Prior Art] Figures 3 (Todoroki) to (C) are schematic process diagrams showing a conventional method for manufacturing a semiconductor device. However, here, the case of a bipolar transistor will be explained as an example. First, an N0 buried layer 2 and a P buried region 3 are formed on a P silicon substrate 1, and an epitaxial layer 4 of N silicon is grown thereon to form a one-isolation oxide film 5. continue,
P-type impurities are diffused by methods such as ion implantation and heat treatment to form a base region 6, and polysilicon 7 is formed on the base region 6.
, an oxide film 8°, and a nitride film G9 [3rd step]
Figure (A) ]. Next, except for the nitrided 1gl9 portion from which the base, emitter, and collector electrodes are taken out, the remaining portions are removed by etching. Next, the remaining nitride film 3 is used as a mask to oxidize the polysilicon 7 to form an oxidized region! 0 and polysilicon 11, 12, 13.14 are formed.

[Same figure (B)]
. Next, after removing all of the oxide fI8 and the nitride M3, polysilicon 12 and 13 are doped with N-type impurities and heat treated to form an N
Ten areas! form 6. Subsequently, an inactive base region 17 is formed by incorporating P-type impurities into polysilicon 11 and 13 and performing heat treatment. And emitter electrode metal 1B. Base electrode metal IE1. Collector electrode metals 20 are formed, and the bipolar transistor is completed [Figure (C)]
]. [Problems to be Solved by the Invention] However, such conventional semiconductor device manufacturing methods have a problem in that the distance between electrode regions cannot be made smaller than the minimum dimension required for mask alignment. Ta. In particular, in the above conventional example, the distance between the emitter region 15 and the inactive base region 17 cannot be made smaller than the minimum dimension for mask alignment in the etching process for partially removing the nitride film 8, and in addition, the oxide region lO Lateral oxidation occurs during the oxidation process to form polysilicon 12.
The distance between the polysilicon and polysilicon 11 and 13 becomes wider. This has resulted in disadvantages such as an increase in base resistance, deterioration of transistor characteristics, and an increase in the area occupied by the element. One possible way to lower the base resistance is to increase the impurity concentration in the base, but this does not solve the above problem because the increase in junction capacitance causes deterioration in transistor characteristics. [Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having at least a control electrode region and a main electrode region. a first diffusion source containing the impurity of the one conductivity type and in contact with the side surface of the first diffusion source via an insulating layer and containing the impurity of the one conductivity type; and a third diffusion source containing a higher concentration than the second diffusion source. One main electrode region is formed by diffusing the impurity from the first diffusion source into the one conductivity type semiconductor layer, and each impurity is diffused into the one conductivity type semiconductor layer from the second and third diffusion sources. This is characterized in that an inactive control electrode region having a higher concentration than the one conductivity type semiconductor layer is formed. [Function] Depending on the thickness of the insulating layer, the main electrode region and #I
m′! Since the distance between the ll pole region and the inactive region is determined, the entire semiconductor device can be miniaturized, and furthermore, the impurity concentration of the inactive region formed by the second diffusion source is Due to the F11 of the type semiconductor layer and the inactive region formed by the third diffusion source, the energy of the 111112a lightning chain is low. Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. s1 Figures (A) to (I) are manufacturing process diagrams showing one embodiment of a method for manufacturing a semiconductor device according to the present invention. First, an N0 buried layer 32 and a P buried region 33 are formed on a P-type silicon substrate 31, and N! ! ! A silicon epitaxial layer 34 is grown to a thickness of about 21 Lm. Further, the nitride IIC (not shown) is patterned to partially form an isolation oxide film 35 of 21 Lm or more. Subsequently, after removing the nitride film, a mask material 36 is applied, openings are formed by patterning, and poron ions are transferred to a concentration I.
Enter with X 1014 am-2 [Figure 1 (A)]
. Next, the mask material 3B is removed, and heat treatment is performed to diffuse the implanted poron ions, resulting in a thickness of 0.2 to 0.8
A P-type base region 37 of 1 Lm is formed. Subsequently, polysilicon 3B having a thickness of 3,000 to 5,000 layers is deposited thereon [FIG. 3(B)]. Next, N-type impurities are diffused into the polysilicon 38 and patterned, and the polysilicon 39 serves as a first diffusion source.
and polysilicon 40 is formed. Subsequently, when oxidation is performed, a thick oxide film 4 is formed on the polysilicon 33 and 40.
1 and 42 are formed and the base region 37 is a single crystal.
A thin oxide film is formed on top. However, as will be described later, the thickness of the oxide film 41 determines the distance between the inactive base region and the emitter region [Figure (C)]
. Next, reactive ion etching (hereinafter referred to as R
IE. ) After removing the thin oxide film on the base region 37, BSG 1II43 is deposited [see the same figure (
D) ]. Next, the BSG film 4 was etched away by 3IE, and BSG was removed as a second diffusion source only on the sidewall of the oxide 1141.
1 (E) leaving H44 and 45]. Next, 4,000 to 7,000 layers of polysilicon 4B are deposited, and poron ions are implanted and diffused therein (CF in the same figure).
]. Next, polysilicon 4B is etched back [FIG.
) ]. Next, the etched back polysilicon 48 is a third diffusion source, and after patterning, thermal oxidation is performed.
By this heat treatment, N-type impurities are diffused from polysilicon 33 and 40 containing N-type impurities, forming N0 emitter regions 47 and N0 regions 48, and forming polysilicon containing P-type impurities (boron). 48 and OSG [144 and 41 which also contain boron], poron is diffused to form a first inactive base region 48 and a second inactive base region 50. However, the impurity concentration of the second inactive base region 50 is between the impurity concentration of the base region 37 (here, ~1Q18) and the impurity concentration of the first inactive base region 49 (here, ~5X1019). . Further, by this thermal oxidation, an oxide film 51 is formed on the polysilicon 48 [FIG. 4(H)]. Finally, openings are formed in the oxide films 44, 42.51 by patterning, and the emitter electrode metal 52. A base electrode metal 53 and a collector electrode metal 54 are each deposited [FIG. 1(1)]. In this way, the bipolar transistor manufactured according to this embodiment has the emitter region 47 and the inactive base region 4.
8 and 50 can be determined by the thickness of the oxide film 41. Furthermore, since the second inactive base region 50 having a higher concentration than the base region 37 is provided, the base resistance can be lowered. FIG. 2 is a partial process diagram showing another embodiment of this example. After depositing polysilicon 36 and diffusing N-type impurities in FIG. 1(B), as shown in FIG. 2(^). The nitride film 6 is patterned by patterning nitride @SO and 81.
Polysilicon 38 is etched using 0 and 61 as masks to form polysilicon 38 and 40. Then, oxidation is performed to form an oxide film 41 with a desired thickness, which determines the distance between the emitter region and the inactive base region. Next, as shown in FIG. 2(B), the thin oxide film on the base region 37 is removed by RIE, and the oxide film 3 on the BSG film 4 is removed.
Then, the same processing as in FIGS. 1(E) to (I) is performed. In this way, the nitrides M60 and 81 are added to the polysilicon 3
Polysilicon 38 is used as a mask when forming 9 and 40, and also as an insulating film.
and 40 patterning steps are simplified. Note that a manufacturing method for the transistor shown in this embodiment with its conductivity type reversed can be very easily conceived from this embodiment. [Effects of the Invention] As explained in detail above, the method for manufacturing a semiconductor device according to the present invention has advantages in that the distance between the main electrode region and the inactive region of the control electrode region is determined by the thickness of the insulating layer. In addition, the entire semiconductor device can be miniaturized, and since the inactive region and the main electrode region do not form a junction, the junction capacitance can be reduced. Roughly speaking, the impurity concentration of the second inactive region formed by the second diffusion source is between the control electrode region and the first inactive region formed by the third diffusion source. The resistance is lower and the characteristics of the device are improved. Therefore, higher integration and higher performance of the semiconductor device can be achieved.

[Brief explanation of drawings]

1(A) to (1) are manufacturing process diagrams showing one embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a partial process diagram showing another embodiment of this embodiment. FIGS. 3A to 3C are schematic process diagrams showing a conventional method for manufacturing a semiconductor device. 31 Dispute・Substrate 34--・Epitaxial layer 3711・Base region 39...Polysilicon (first diffusion source) 44, 45-
@・Polysilicon (second diffusion source) 46...Fist polysilicon (third diffusion source) 47...Emitter region 49...First inactive base region 50...Second inactive base region 1st Figure 2

Claims (1)

[Claims] (1) In a method of manufacturing a semiconductor device having at least a control electrode region and a main electrode region, a first diffusion source containing an impurity of an opposite conductivity type is provided on a semiconductor layer of one conductivity type, and an insulated side surface of the first diffusion source is provided. a second diffusion source containing the impurity of the one conductivity type and in contact with each other through a layer;
forming a third diffusion source that is in contact with the second diffusion source and contains impurities of the one conductivity type at a higher concentration than the second diffusion source; and directing the impurities from the first diffusion source to the one conductivity type semiconductor layer. One main electrode region is formed by diffusion, and each impurity is diffused into the one conductivity type semiconductor layer from the second and third diffusion sources to form an inactive control electrode with a higher concentration than the one conductivity type semiconductor layer. A method of manufacturing a semiconductor device, comprising forming a region.