JPH03272144A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a bipolar transistor, which is good in characteristics, by a method wherein the junction depth of an emitter region is formed roughly constant at the central part under an emitter opening and the periphery of the central part. CONSTITUTION:In the case of diffusion of an impurity in an emitter region, as an impurity diffusion source comes into contact to a sidewall 19'' of a concentration identical with that of an impurity in the diffusion source, an impurity sucking-out rate of the wall 19'' is low in the case of diffusion. Accordingly, even if the diffusion of the impurity in the emitter region is thin and an emitter width is narrow, the amount of the impurity, which is diffused in the wall 19'', of a doped impurity can be ignored and the amount of diffusion in a substrate can be sufficiently obtained. Thereby, a diffused layer can be formed in a normal depth even on the side which is near the wall 19'' in the emitter region E, a junction depth of the region E is formed roughly constant at the central part under an emitter opening and the peripheral part of the central part and there is not the fact that a switching time takes long and a current amplification factor and a cut-off frequency are reduced. Thereby, good characteristics are obtained for a bipolar transistor.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to an emitter region of a bipolar transistor or an insulated gate type (MOS) transistor. The present invention relates to a drain region or a source region and a method for forming the same.

(Prior art) Figure 4 shows an example of a conventional bipolar transistor, which is a self-line type NPN with a double-layer polysilicon structure.
It shows a cross-sectional structure of a transistor. Here, 40 is a P type semiconductor substrate, 41 is an N+ buried layer, 42 is an N- epitaxial layer, 43 is a deep N+ region, 44 is a field insulating film for element isolation, EB is a P+ type external base region, and IB is E is a P- type internal base region, E is an N+ type emitter region, 45 is an external base extraction electrode made of a P-type polysilicon film, 46 is an insulating film covering the external base extraction electrode 45, and 47 is formed on the side wall of the emitter opening. A sidewall 48 for defining an emitter opening is made of non-doped polysilicon, and 48 is an emitter extraction electrode made of an N-type polysilicon film. The sidewall 47 serves as a mask for etching the insulating film on the substrate within the emitter opening, and consequently defines the size of the contact between the emitter extraction electrode 48 and the emitter region E. Note that the external base region EB has an external base extraction electrode (
The emitter region E is formed by diffusion of P-type impurities from the P-type polysilicon film), and the emitter region E is formed by the emitter extraction electrode (
It is formed by diffusion of N-type impurities from the N-type polysilicon film.

According to the above structure, the emitter region and the base region can be formed in a self-aligned manner without requiring mask alignment, and no mask alignment margin is required between the external base region EB and the emitter region E. Yes, the external base resistance is reduced. Furthermore, the emitter region E is formed by the sidewall 4.
7 makes the interval narrower than the interval between the external base extraction electrodes 45 on the glass mask, so that the internal base resistance also becomes small. This provides extremely excellent properties.

However, in the above structure, the emitter extraction electrode 48, which serves as an emitter impurity diffusion source, is in contact with the emitter opening defining sidewall 47 made of non-doped polysilicon.
987. Bipolar C1rcuits and
Technology MeeLing, p, I78
B, Y, ) Twang, etc.), the sidewall 47 sucks out impurities from the emitter extraction electrode 48 during emitter impurity diffusion. In this case, the emitter extraction electrode 48 may be thin or thin, but if the emitter width is narrow, the amount of impurities doped in the emitter extraction electrode 48 that diffuses into the sidewall 47 cannot be ignored, and the amount of diffusion into the substrate becomes small. Become. As a result, the emitter impurity concentration decreases on the side of the emitter region E closer to the sidewall 47, or the emitter junction depth becomes shallower, the switching time of the transistor increases, and the current amplification factor and cutoff frequency decrease. Such inconveniences may occur.

FIG. 5 shows an enlarged view of the vicinity of the emitter region in FIG. 4, and shows that the junction depth of the emitter region is significantly shallower at the periphery than at the center below the emitter opening. I understand.

Note that in the drain region or source region of a conventional MO3 type transistor, similarly to the above, the junction depth of the region is significantly shallower in the peripheral region than in the central region under the drain or source opening.

(Problems to be Solved by the Invention) As described above, in conventional semiconductor devices, the junction depth is shallow on the side of the emitter region close to the emitter sidewall, and the junction depth is shallow on the side of the emitter region close to the emitter sidewall, and There is a problem in that the junction depth becomes shallower on the side closer to the wall or source sidewall.

The present invention has been made to solve the above-mentioned problems, and its purpose is to make the junction depth of the emitter region approximately constant between the central part and the peripheral part under the emitter opening, or to It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, in which the junction depth is approximately constant between the central portion under the drain opening or the source opening and the peripheral portion, and the characteristics are good.

[Structure of the Invention] (Means for Solving the Problems) In the semiconductor device of the present invention, the junction depth of the emitter region in a bipolar transistor having a sidewall defining an emitter opening is equal to that in the central part below the emitter opening and in the peripheral part. It is characterized by being almost constant.

Further, in the semiconductor device of the present invention, the junction depth of the drain region or the source region in a MOS transistor having a sidewall defining a drain opening or a source opening between two gate electrodes is at a central portion below the drain opening or the source opening. It is characterized by being almost constant between the area and the periphery.

Further, in the method for manufacturing a semiconductor device of the present invention, when forming a sidewall for defining an emitter opening in the process of forming a bipolar transistor, the same impurity is added so as to have the same concentration as the impurity of an emitter impurity diffusion source that will be formed later. It is characterized by the introduction of

Further, in the method of manufacturing a semiconductor device of the present invention, when forming a sidewall for defining a drain opening or a source opening in the process of forming a MOS transistor, impurities of a drain impurity diffusion source or a source impurity diffusion source that will be formed later can be removed. It is characterized in that the same impurity is introduced so as to have a concentration equal to that of .

(Function) In the semiconductor device of the first invention, the junction depth of the emitter region is almost constant between the central part and the peripheral part under the emitter opening,
A bipolar transistor with good characteristics is realized.

Further, in the semiconductor device of the second invention, the junction depth of the drain region or the source region is almost constant between the central part under the drain opening or the source opening and the peripheral part, and a MOS transistor with good characteristics is realized. .

Further, in the method for manufacturing a semiconductor device according to the third aspect of the invention, when diffusing an emitter impurity in the step of forming a bipolar transistor, the emitter impurity is introduced into the sidewall so as to have the same impurity concentration as the impurity of the emitter impurity diffusion source. Since the diffusion sources are in contact, the sidewalls are less likely to suck out impurities from the emitter impurity diffusion source.

Therefore, even if the emitter impurity diffusion source is thin and the emitter width is narrow, the amount of impurities doped in the emitter impurity diffusion source that diffuses into the sidewalls can be ignored, and the amount diffused into the substrate can be sufficiently obtained. It will be done. This results in
A diffusion layer can be formed at a normal depth even on the side of the emitter region close to the sidewall, and the junction depth of the emitter region is approximately constant between the central portion under the emitter opening and the peripheral portion.

Further, the method for manufacturing a semiconductor device according to the fourth invention is a MOS)
During drain diffusion or source diffusion in the transistor formation process, the drain impurity diffusion source or source impurity diffusion source is placed in the sidewall into which the same impurity is introduced so as to have the same impurity concentration as that of the drain impurity diffusion source or source impurity diffusion source. Because of the contact, the sidewalls are less likely to suck out impurities from the drain impurity diffusion source or the source impurity diffusion source. Therefore, even if the drain impurity diffusion source or source impurity diffusion source is thin and the drain or source opening is narrow, impurities doped in the drain impurity diffusion source or source impurity diffusion source will not diffuse into the sidewall. can be prevented, and a sufficient amount of diffusion to the substrate can be obtained. As a result, a diffusion layer can be formed at a normal depth even on the side of the drain or source region near the sidewall, and the junction depth of the drain or source region can be adjusted between the central part under the drain opening or the source opening and the peripheral part. becomes almost constant.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIGS. 1(a) to (e) show the cross-sectional structure of a semiconductor substrate in the manufacturing process of a self-line type NPN transistor with a two-layer polysilicon structure. ), a method of forming an NPN) transistor will be described.

First, as shown in FIG. 1(a), a P-type semiconductor substrate 10
has an N- epitaxial layer 11 on the surface, and an N+ layer inside.
A semiconductor substrate 13 having a mold-shaped buried layer 12 is formed.

The main surface of this semiconductor substrate 13 (N-epitaxial layer 1
1), a field insulating film 13 is formed by selective oxidation in a manner surrounding a certain predetermined region, and a deep N+ region reaching the N' buried layer 12 is formed in a part of the N- epitaxial layer 11]4
form. Next, a relatively thin oxide film 1 is applied to the entire surface of the substrate.
Further, an oxide film 1 is formed on the surface of the area where the element is to be formed.
5 is removed, and a first semiconductor film (in this example, a P-type impurity (e.g., boron) is added to at least the region where an element is to be formed on the surface of the N-epitaxial layer 11 to serve as an external base extraction electrode and an external base diffusion source) is removed. A first polysilicon film 16 and a first insulating film 17 made of an oxide film by CVD (vapor phase growth) are sequentially formed.

Next, as shown in FIG. 1(b), the first insulating film 17
After patterning the first polysilicon film 16 to form self-line openings, annealing is performed. As a result, the first polysilicon film is exposed to the external base extraction electrode 1.
6'', and a P'' external base region EB is formed in the element formation area on the main surface of the semiconductor substrate. Thereafter, a second insulating film 18 is formed on the entire surface of the substrate so as to cover the first insulating film 17, the external base extraction electrode 16'', and the main surface of the semiconductor substrate exposed in the SELF 3 line opening.

Next, a second semiconductor film (second polysilicon film in this example) 19 is formed over the entire surface of the substrate to form a sidewall that defines the emitter opening. In this case, impurities are introduced into one of the second polysilicon films so that the impurities are the same and have the same concentration as the impurities of the emitter extraction electrode that will be formed later. As for the method of introducing this impurity, ■
Either by introducing a gas containing impurities when forming one second polysilicon film by CVD method, or by introducing impurities into the film by ion implantation after depositing one second polysilicon film, and then by thermal diffusion. Is the impurity concentration in the film uniform?■
There is a method in which, after depositing one second polysilicon film, an insulating film (not shown) containing impurities is deposited, and the impurities are introduced into the film from this insulating film by thermal diffusion.

Note that the impurity concentration in the second polysilicon film 19 needs to be uniform, and when introducing the impurity, the second insulating film 18 prevents diffusion to the underlying side. Accordingly, it is possible to easily equalize the impurity concentration in the film.

Note that before or after forming the second insulating film 18,
A P-type impurity is ion-implanted into the substrate in the inner region surrounded by the external base extraction electrode 16'' to form a P- internal base region IB.

Next, as shown in FIG. 1(C), the second polysilicon film 19 is etched back to form a side wall 19''. Note that the etching in this step is performed to precisely define the dimensions of the transistor. Therefore, an anisotropic etching method is used.

Next, as shown in FIG. 1(d), the exposed second insulating film 18 is removed using the sidewall 19'' as a mask.
(If there is an oxide film 15 under it, this oxide film 15
Also included. ) is etched back by anisotropic etching to provide an emitter opening and also to form the deep N+ region 14.
expose.

Next, as shown in FIG. 1(e), a third poly-5 silicon film 20 which will serve as the emitter 1 output electrode and emitter diffusion source is deposited. In this case, the impurity is introduced into the third polysilicon film 20 serving as the emitter diffusion source by introducing, for example, arsenic as an N-type impurity by an ion implantation method, but other impurities may be used. Next, on the top surface of the substrate, an oxide film (
(not shown), heat treatment is performed to perform emitter diffusion to form an emitter region E. Thereafter, the third polysilicon film 20 is patterned to form an emitter extraction electrode 20''.

Next, the first oxide film 17 on the external base extraction electrode 16''
A base electrode opening (not shown) is provided by selectively removing the base electrode, and a metal wiring (usually aluminum wiring) is formed to complete the NPN transistor.

FIG. 2 shows an enlarged view of the vicinity of the emitter region E in FIG. It has become.

That is, in the step 6 of forming the NPN transistor in the above embodiment, when diffusing the emitter impurity, the emitter impurity diffusion source is brought into contact with the sidewall 19'' into which the same impurity is introduced so as to have the same impurity concentration as that of the emitter impurity diffusion source. Therefore, the degree to which the sidewall 19'' sucks out impurities from the emitter impurity diffusion source during emitter impurity diffusion is low. Therefore, even if the emitter impurity diffusion source is thin or the emitter width is narrow,
Of the impurities doped in the emitter impurity diffusion source, the amount diffused into the sidewall 19'' can be ignored, and a sufficient amount of diffusion into the substrate can be obtained. A diffusion layer can be formed at a normal depth even on the side, and the junction depth of the emitter region is almost constant between the center and the periphery under the emitter opening, which increases the switching time of the transistor and reduces the current amplification factor and cutoff. Inconveniences such as a decrease in frequency do not occur.

FIG. 3 shows a cross-sectional structure of a MOS transistor according to another embodiment of the present invention, in which 30 is a semiconductor 7 substrate, 31 is a gate insulating film on the surface of the substrate, 32 and 3
3 is a gate electrode, 34 is an insulating film on the gate electrode/substrate surface, and 35 is the above two gate electrodes 32 and 3.
3, and is formed on the side walls of the two gate electrodes 32 and 33 with the insulating film 34 interposed therebetween.

36 is a drain region or source region, 37 is a drain wiring or source wiring (polysilicon), and 38 is a protective insulating film.

In order to form the MOS transistor, there are two steps: forming a field insulating film (not shown) around the area on the main surface of the semiconductor substrate 30 where the element is to be formed; A step of forming a gate insulating film 31 on the main surface of the semiconductor substrate, and forming gate electrodes 32, 33, and 32 on the gate insulating film 31 on a region where an element is to be formed on the main surface of the semiconductor substrate.
. . and the step of forming the gate electrodes 32, 33 .
・A step of forming a first insulating film 34 on the top and substrate surface, and a step of forming a first insulating film 34 on the opposing sidewalls of the gate electrodes 32, 33 at adjacent locations 8 of the gate electrodes 32, 33... A process of forming a sidewall 35 doped with the same impurity as the impurity concentration of the drain wiring or source wiring 37 formed in the first insulating film 34 and the gate insulating film 34 using the sidewall 35 as a mask. A step of removing the film 31 to form a drain opening or a source opening, forming a third semiconductor film for drain diffusion or source diffusion in contact with the drain opening or source opening, and performing drain diffusion or source diffusion to form a drain. The steps of forming a region or source region 36 and patterning the third semiconductor film to form a drain wiring or source wiring 37 may be sequentially performed.

In the above MO8) transistor formation process, the same impurity is introduced into the side wall 3 so as to have the same concentration as the impurity of the drain impurity diffusion source or the source impurity diffusion source during drain diffusion or source diffusion.
Since the drain impurity diffusion source or the source impurity diffusion source 9 is in contact with the drain impurity diffusion source 5, the degree to which the sidewall 35 sucks out impurities from the drain impurity diffusion source or the source impurity diffusion source is low. Therefore, even if the drain impurity diffusion source or the source impurity diffusion source is thin and the drain or source opening is narrow, the impurity doped in the drain impurity diffusion source or the source impurity diffusion source is prevented from diffusing into the sidewall 35. This can be prevented and a sufficient amount of diffusion to the substrate can be obtained. As a result, a diffusion layer can be formed at a normal depth even on the side of the drain region or source region 36 that is close to the sidewall 35, and the junction depth of the drain region or source region 36 is at the center below the drain or source opening. It becomes almost constant between the area and the periphery.

Although the above embodiments have been described with respect to discrete devices, the present invention also applies to bipolar type, MOS (CMOS) type, or bipolar M
The present invention can also be applied to OS (CMOS) type semiconductor integrated circuits and methods of manufacturing the same.

0 [Effects of the Invention] As described above, according to the present invention, the junction depth of the emitter region is approximately constant between the central part and the peripheral part under the emitter opening, or the junction depth of the drain region or the source region is It is possible to realize a semiconductor device and a method for manufacturing the same, which have good characteristics in which the characteristics are substantially constant between the central portion under the drain opening or the source opening and the peripheral portion.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are diagrams showing the cross-sectional structure of a semiconductor substrate at each step in a method for forming a bipolar transistor according to an embodiment of the present invention, and FIG. A cross-sectional view showing an enlarged view of the vicinity of the emitter region,
FIG. 3 shows the cross-sectional structure of a MOS transistor according to another embodiment of the present invention.
12... N- epitaxial layer, 13... Field insulating film, 14... Deep N+ region, 15... Oxide film, 1 16... First polysilicon film, 16''... External base Extraction electrode, ]7... first insulating film, 18... second
Insulating film, one...second polysilicon film, 19"...
Side wall, 20#... Emitter extraction electrode, E
B...external base area, IB...internal base area,
E...Emitter area.

Claims (4)

[Claims] (1) A bipolar semiconductor device having a sidewall defining an emitter opening, characterized in that the junction depth of the emitter region of the bipolar transistor is approximately constant between a central portion under the emitter opening and a peripheral portion. Device. (2) In an insulated gate semiconductor device having a sidewall defining a drain opening or source opening between two gate electrodes, the junction depth of the drain region or source region of a field effect transistor is below the drain opening or source opening. A semiconductor device characterized in that the temperature is almost constant between a central portion and a peripheral portion. (3) When forming a bipolar transistor, a step of forming a field insulating film around a region where an element is to be formed on the main surface of the semiconductor substrate; forming a first semiconductor film that also serves as a diffusion source; forming a first insulating film on the first semiconductor film; forming the first insulating film and the first semiconductor film on a region where an emitter is to be formed; forming a second insulating film on each of the first insulating film, the first semiconductor film and the main surface of the semiconductor substrate exposed in the self-aligning opening; , forming a sidewall doped with the same impurity as the impurity of the emitter extraction electrode to be formed later, inside the self-aligned opening; and using this sidewall as a mask, the bottom surface of the self-aligned opening. forming an emitter opening by removing the second insulating film, and forming an internal base region on the substrate surface in an inner region surrounded by the external base extraction electrode before or after forming the second insulating film; and a step of forming a third semiconductor film for emitter diffusion in contact with the emitter opening, performing emitter diffusion, and patterning the third semiconductor film to form an emitter extraction electrode. A method for manufacturing a semiconductor device. (4) When forming an insulated gate field effect transistor, a step of forming a field insulating film around a region where an element is to be formed on the main surface of the semiconductor substrate, and a step of forming a gate insulating film on the region where an element is to be formed on the main surface of the semiconductor substrate. a step of forming a gate electrode on a gate insulating film on a region where an element is to be formed on the main surface of the semiconductor substrate; and a step of forming a first insulating film on the gate electrode and the surface of the substrate. , Forming sidewalls doped with the same impurity so as to have the same concentration as the impurity of the drain wiring or source wiring to be formed later, on the opposing sidewalls of adjacent predetermined gate electrodes among the gate electrodes. a step of removing the first insulating film and the gate insulating film using the sidewall as a mask to form a drain opening or a source opening; and a step of forming a drain opening or a source opening in contact with the drain opening or the source opening. forming a third semiconductor film;
A method for manufacturing a semiconductor device, comprising the steps of forming a drain region or a source region by performing drain diffusion or source diffusion, and patterning the third semiconductor film to form a drain wiring or a source wiring.