KR950005477B1 - Making method of semiconductor device - Google Patents
Making method of semiconductor device Download PDFInfo
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- KR950005477B1 KR950005477B1 KR1019920017189A KR920017189A KR950005477B1 KR 950005477 B1 KR950005477 B1 KR 950005477B1 KR 1019920017189 A KR1019920017189 A KR 1019920017189A KR 920017189 A KR920017189 A KR 920017189A KR 950005477 B1 KR950005477 B1 KR 950005477B1
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims description 33
- 238000009792 diffusion process Methods 0.000 claims abstract description 46
- 239000012535 impurity Substances 0.000 claims abstract description 45
- 239000002019 doping agent Substances 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 description 5
- 230000010354 integration Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
Abstract
Description
제1도는 종래의 PMOS트랜지스터를 도시한 단면도.1 is a cross-sectional view showing a conventional PMOS transistor.
제2도 및 제3도는 본 발명의 제1실시예를 도시한 도면.2 and 3 show a first embodiment of the present invention.
제4도 및 제5도는 본 발명의 제2실시예를 도시한 도면.4 and 5 show a second embodiment of the present invention.
본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 PMOS트랜지스터의 소오스/드레인 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a source / drain of a PMOS transistor.
현재 PMOS트랜지스터에 있어서 소오스 및 드레인영역의 형성은 BF2 +를 이온주입하여 얕은 접합(Shallow Junction)을 형성하고 있으나, 반도체소자가 더욱 고집적화됨에 따라 더욱 더 얕은 접합의 형성은 어렵게 되고 있다.Formation of source and drain regions in the PMOS transistor are ion-implanted by a BF 2 +, but to form a shallow junction (Shallow Junction), formation of the more shallow junction as the semiconductor device is more highly integrated may become difficult.
제1도를 참조하여 종래의 PMOS트랜지스터의 소오스 및 드레인영역 형성방법을 설명하면 다음과 같다.Referring to FIG. 1, a method of forming a source and a drain region of a conventional PMOS transistor is described below.
반도체기판(1)상에 게이트산화막(2)을 형성하고 이어서 도전물질, 예컨대 폴리실리콘을 침적한 후 이를 소정패턴으로 패터닝하여 게이트전극(3)을 형성한 다음, BF2 +또는 B+를 이온주입하여 P+영역으로 된 소오스 및 드레인영역(4)을 형성하고 나서 게이트전극(3) 측벽에 게이트 측벽스페이서(5)을 형성한다. 상기 소오스 및 드레인영역(4)의 접합깊이의 조절은 BF2 +또는 B+의 이온주입시의 이온주입에너지에 의해 결정된다.Forming a gate oxide film 2 on a semiconductor substrate 1 and then a conductive material, for example, is deposited a polysilicon which it formed a gate electrode 3 is patterned in a predetermined pattern, and then, BF 2 + or B + ion After implantation, the source and drain regions 4 formed of P + regions are formed, and then gate sidewall spacers 5 are formed on the sidewalls of the gate electrodes 3. The control of the junction depth of the source and drain regions 4 is determined by the ion implantation energy at the time of ion implantation of BF 2 + or B + .
상기 종래의 PMOS트랜지스터의 소오스 및 드레인 형성방법에 있어서는 반도체소자가 고집적화되어 감에 따라 이온주입에 의한 얕은 접합의 형성이 어려워지고, 또한 주입된 불순물이온들이 열처리공정에 의해 횡방향 및 종방향으로 확산되어 고집적화에 따라 미세화된 반도체소자에 있어서 펀치쓰루(Punchthrough)특성이 나빠지게 된다.In the conventional method of forming a source and a drain of a PMOS transistor, as the semiconductor device becomes highly integrated, it is difficult to form a shallow junction by ion implantation, and implanted impurity ions diffuse in the lateral and longitudinal directions by a heat treatment process. As a result, the punchthrough characteristics of the semiconductor device miniaturized due to high integration are deteriorated.
본 발명은 상술한 문제점을 해결하기 위한 것으로, 펀치쓰루 특성을 향상시킴으로써 반도체소자의 고집적화에 대응할 수 있는 반도체소자의 얕은 접합의 불순물확산층 형성방법을 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method for forming an impurity diffusion layer in a shallow junction of a semiconductor device that can cope with high integration of the semiconductor device by improving punch-through characteristics.
상기 목적을 달성하기 위해 본 발명에 의한 반도체장치의 제조방법은 반도체기판 소정부분에 이온주입에 의해 형성된 P+형 불순물확산영역들과 상기 서로 인접한 P+형 불순물확산영역 사이의 반도체기판상에 형성된 게이트절연막 및 게이트전극으로 구성된 반도체장치의 제조방법에 있어서, 상기 P+형 불순물확산영역하부와 하부측의 측면의 일부를 감싸도록 N+형 불순물확산영역을 형성하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is provided on a semiconductor substrate between P + type impurity diffusion regions formed by ion implantation into a predetermined portion of the semiconductor substrate and the adjacent P + type impurity diffusion regions. A method of manufacturing a semiconductor device comprising a gate insulating film and a gate electrode, characterized in that an N + type impurity diffusion region is formed so as to surround a portion of the lower side of the P + type impurity diffusion region and a lower side thereof.
상기 P+형 불순물확산영역 하부 및 측면에 N+형 불순물확산영역을 형성하는 공정은 반도체기판상에 게이트산화막과 게이트전극을 소정 공정에 의해 형성한 후, P형 도판트(Dopant)인 BF2 +또는 B+이온을 일정깊이로 반도체기판내에 주입하여 P+형 불순물확산영역을 형성한다. 이어서 상기 게이트전극 측벽에 CVD(Chemical Vapor Deposition)산화막이나 Si3N4로 이루어진 측벽스페이서을 형성한 후, N형 도판트인 Aa+또는 P+를 일정각도 이상 기울여서(Tilt) 이온주입함으로써 상기 P+형 불순물확산영역의 하부와 측면의 반정도를 감싸는 N+형 불순물확산영역을 형성한다.Wherein the P + type impurity forming the diffusion region bottom and side N + type diffusion region on the after the gate oxide film and gate electrode on a semiconductor substrate formed by a predetermined process, P-type dopant (Dopant) BF 2 + Or B + ions are implanted into the semiconductor substrate at a predetermined depth to form a P + type impurity diffusion region. Subsequently, a sidewall spacer made of a CVD (Chemical Vapor Deposition) oxide film or Si 3 N 4 is formed on the sidewall of the gate electrode, and the ion is implanted by tilting the N-type dopant Aa + or P + by a predetermined angle or more to form the P + type. An N + type impurity diffusion region is formed to cover half of the lower and side surfaces of the impurity diffusion region.
또한, 상기 P+형 불순물확산영역 하부 및 측면에 N+형 불순물확산영역을 형성하는 공정은 반도체기판상에 게이트산화막과 게이트전극을 소정 공정에 의해 형성하고 상기 게이트전극 측벽에 측벽스페이서를 형성한 후, N형 도판트인 As+또는 P+를 일정각도 이상 기울여서(Tilt) 이온주입하여 N+형 불순물확산영역을 먼저 형성한 다음 이어서 상기 측벽스페이서를 제거하고 난후 P형 도판트(Dopant)인 BF2 +또는 B+이온을 일정깊이로 반도체기판내에 주입하여 P+형 불순물확산영역을 형성한다.Further, the step of forming the P + -type impurity diffusion region bottom and side N + type diffusion region on the and the gate oxide film and gate electrode on a semiconductor substrate formed by a predetermined process of forming a sidewall spacer on the gate electrode side wall Then, the ion implantation is performed by tilting the N-type dopant As + or P + by a predetermined angle or more to form an N + -type impurity diffusion region, and then removing the sidewall spacers, and then the B-type dopant BF. 2 + or by injection into the semiconductor substrate with B + ions at a predetermined depth to form a P + type impurity diffusion regions.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
제2도 및 제3도는 본 발명의 제1실시예에 의한 PMOS트랜지스터의 소오스 및 드레인영역 형성방법을 나타낸 것이다.2 and 3 illustrate a method of forming a source and a drain region of a PMOS transistor according to a first embodiment of the present invention.
반도체기판(11)상에 열산화공정에 의해 게이트산화막(12)을 형성한 후, 상기 게이트산화막(12)상에 폴리실리콘을 침적하여 이를 패터닝하여 게이트전극(13)을 형성한다. 이어서 BF2 +또는 B+중의 어느 하나를 이온주입하여 상기 반도체기판내에 소정깊이를 갖는 P+형 불순물확산영역(14)을 형성한다(제2도).After the gate oxide film 12 is formed on the semiconductor substrate 11 by a thermal oxidation process, polysilicon is deposited on the gate oxide film 12 and patterned to form the gate electrode 13. Is then to ion implantation of BF 2 +, or either B + forms the P + type diffusion region 14 having a predetermined depth in the semiconductor substrate (FIG. 2).
다음에 상기 결과물상에 절연막으로서, 예컨대 HTO(High Temperature Oxide) 또는 Si3N4중의 어느 하나를 침적하고 이를 전면 에치백하여 상기 게이트전극(13)측벽에 측벽스페이서(15)를 형성한다. 이어서 As+또는 P+중의 어느 하나를 일정각도 이상으로 경사지게 이온주입하여 상기 P+형 불순물확산영역(14)하부 및 측면의 일부분에 이르기까지 N+형 불순물확산영역(16)을 형성한다(제3도). 이때, 상기 N+형 불순물확산영역(16)에 의해 둘러싸여지지 않은 상기 P+형 불순물확산영역(14)의 측면부위의 깊이(A)가 게이트채널 깊이가 된다.Next, one of HTO (High Temperature Oxide) or Si 3 N 4 is deposited on the resultant material and etched back to form a sidewall spacer 15 on the side wall of the gate electrode 13. Subsequently, ion implantation of either As + or P + is inclined at a predetermined angle or more to form the N + type impurity diffusion region 16 up to the lower part of the P + type impurity diffusion region 14 (the first). 3 degrees). At this time, the depth A of the side portion of the P + type impurity diffusion region 14 which is not surrounded by the N + type impurity diffusion region 16 becomes the gate channel depth.
이상과 같이 본 발명의 제1실시예에 의하면 PMOS트랜지스터의 소오스 및 드레인영역인 P+형 불순물확산영역의 하부 및 일부측면을 반대도전형인 불순물영역인 N+형 불순물확산영역이 감싸도록 함으로써 반도체소자의 미세화에 따라 일어날 수 있는 펀치쓰루현상을 방지할 수 있게 된다.As described above, according to the first embodiment of the present invention, a semiconductor is formed by covering the lower and partial sides of the P + type impurity diffusion region, which is the source and drain regions of the PMOS transistor, with the N + type impurity diffusion region, which is the opposite conductivity type, covered. It is possible to prevent the punch-through phenomenon that can occur due to the miniaturization of the device.
다음에 제4도를 참조하여 본 발명의 제2실시예에 의한 PMOS트랜지스터의 소오스 및 드레인영역 형성방법을 설명한다.Next, a method of forming a source and a drain region of a PMOS transistor according to a second embodiment of the present invention will be described with reference to FIG.
반도체기판(11)상에 열산화공정에 의해 게이트산화막(12)을 형성한 후, 상기 게이트산화막(12)상에 폴리실리콘을 침적하여 이를 패터닝하여 게이트전극(13)을 형성한 다음, 결과물상에 절연막으로서, 예컨대 Si3N4를 침적하고 이를 전면에치백하여 상기 게이트전극(13)측벽에 측벽스페이서(15)를 형성한다. 이어서 As+또는 P+중의 어느 하나를 일정각도 이상으로 경사지게 이온주입하여 상기 N+형 불순물확산영역(16)을 먼저 형성한다(제4도).After the gate oxide film 12 is formed on the semiconductor substrate 11 by a thermal oxidation process, polysilicon is deposited on the gate oxide film 12 and patterned to form a gate electrode 13, and then As an insulating film, for example, Si 3 N 4 is deposited and back-etched to form a sidewall spacer 15 on the side wall of the gate electrode 13. Subsequently, either N + -type impurity diffusion region 16 is first formed by ion implantation of either As + or P + inclined at a predetermined angle or more (FIG. 4).
다음에 상기 측벽스페이서를 인산을 이용하여 제거한 후, BF2 +또는 B+중의 어느 하나를 이용하여 상기 먼저 형성된 N+형 불순물확산영역의 깊이보다 얕게 형성되도록 이온주입에너지를 조절하여 이온주입을 행하여 상기 반도체기판내에 소정깊이를 갖는 P+형 불순물확산영역(14)을 형성한다(제5도). 이때, 상기 제1실시예의 경우와 마찬가지로 상기 N+형 불순물확산영역(16)에 의해 둘러싸여지지 않은 상기 P+형 불순물확산영역(14)의 측면부위의 깊이(A)가 게이트채널 깊이가 된다.Next, the sidewall spacers are removed using phosphoric acid, and ion implantation energy is adjusted by using either BF 2 + or B + to control the ion implantation energy so as to be shallower than the depth of the previously formed N + type impurity diffusion region. A P + type impurity diffusion region 14 having a predetermined depth is formed in the semiconductor substrate (FIG. 5). At this time, as in the case of the first embodiment, the depth A of the side portion of the P + type impurity diffusion region 14 which is not surrounded by the N + type impurity diffusion region 16 becomes the gate channel depth.
이상과 같이 본 발명의 제2실시예에 의하면, PMOS트랜지스터의 소오스/드레인영역인 P+형 불순물확산영역을 형성하기 전에 먼저 반대도전형의 불순물영역인 N+형 불순물확산영역을 형성하게 되므로 N형 도판트의 이온주입에 의한 Pre-Amophization 효과에 의해 P+형 불순물확산영역의 접합깊이를 더욱 얇게 조절할 수 있으며, P+형 불순물확산영역의 하부 및 일부측면을 반대도전형의 불순물영역인 N+형 불순물확산영역이 감싸고 있으므로 게이트전극에 인가전압이 가해졌을 때 소오스/드레인영역에서의 P+디플리션(Depletion)이 억제되므로 주변소자와의 분리특성이 향상된다.As described above, according to the second embodiment of the present invention, before forming the P + type impurity diffusion region as the source / drain region of the PMOS transistor, the N + type impurity diffusion region as the opposite conductivity type is first formed. Pre-Amophization effect by ion implantation of the type dopant makes it possible to adjust the junction depth of the P + type impurity diffusion region thinner, and the lower part and some sides of the P + type impurity diffusion region are N impurity regions of opposite conductivity type. Since the + type impurity diffusion region is enclosed, P + depletion in the source / drain region is suppressed when an applied voltage is applied to the gate electrode, thereby improving separation characteristics from peripheral devices.
이상 상술한 바와 같이 본 발명에 의하면, PMOS트랜지스터의 소오스/드레인영역 형성에 있어서 더욱 얕은 접합을 얻을 수 있을뿐 아니라, 펀치쓰루 특성 및 소자간 분리특성을 향상시킬 수 있으므로 반도체소자의 고집적화에 기여할 수 있게 된다.As described above, according to the present invention, not only a shallower junction can be obtained in forming the source / drain regions of the PMOS transistor, but also the punch-through characteristics and the isolation characteristics between devices can be improved, thereby contributing to the high integration of semiconductor devices. Will be.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920017189A KR950005477B1 (en) | 1992-09-21 | 1992-09-21 | Making method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920017189A KR950005477B1 (en) | 1992-09-21 | 1992-09-21 | Making method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940008122A KR940008122A (en) | 1994-04-28 |
| KR950005477B1 true KR950005477B1 (en) | 1995-05-24 |
Family
ID=19339871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920017189A KR950005477B1 (en) | 1992-09-21 | 1992-09-21 | Making method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR950005477B1 (en) |
-
1992
- 1992-09-21 KR KR1019920017189A patent/KR950005477B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR940008122A (en) | 1994-04-28 |
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