JPH02244636A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02244636A
JPH02244636A JP6421189A JP6421189A JPH02244636A JP H02244636 A JPH02244636 A JP H02244636A JP 6421189 A JP6421189 A JP 6421189A JP 6421189 A JP6421189 A JP 6421189A JP H02244636 A JPH02244636 A JP H02244636A
Authority
JP
Japan
Prior art keywords
layer
oxide film
polycrystalline
opening
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6421189A
Other languages
Japanese (ja)
Inventor
Hiromi Hayashi
林 浩美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6421189A priority Critical patent/JPH02244636A/en
Publication of JPH02244636A publication Critical patent/JPH02244636A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To contrive the fine formation of a bipolar transistor and an increase in the uniformity of the characteristics of the transistor by a method wherein an external base, an internal base and an emitter are formed in a self-alignment manner to a field oxide film. CONSTITUTION:A field oxide film 2 and a P-type polycrystalline Si layer 3, subsequently, a CVD oxide film 4 are formed on an N-type substrate 1. Then, the film 2, the layer 3 and the film 4 are simultaneously subjected to selective etching and removed to form an opening part. Then, boron is diffused in the substrate 1 through a P-type polycrystalline Si layer 5 selectively formed on the sidewall of the opening part to form an external base region 6 in a self- alignment manner to the film 2. Then, after an oxide film 7 is formed in the opening part, boron is implanted in the substrate 1 using the layer 5 as a mask to form an internal base region 8. Then, after a CVD oxide film 9 is formed on the whole surface, a polycrystalline Si layer 10 is selectively formed and moreover, a polycrystalline Si layer 11 is grown and arsenic is diffused to form an emitter region 12.

Description

【発明の詳細な説明】 〔概 要〕 バイポーラトランジスタの製造方法に関し、外部ベース
、内部ベース及びエミッタをフィールド酸化膜に対して
自己整合的に形成する方法を提供することを目的とし、 一導電型基板上に形成されたフィールド酸化膜、反対導
電型多結晶siN及び絶縁膜からなる多層膜を選択的に
エッチング・除去して開口部を形成する工程と、前記開
口部の多層膜側壁に選択的に形成した第1の反対導電型
多結晶Si層から反対導電型不純物を基板内に拡散させ
ることにより外部ベース領域を形成する工程と、前記開
口部内に酸化膜を形成した後、前記第1の多結晶Si層
をマスクとして基板内に反対導電型不純物を打ち込み前
記外部ベース領域に接する内部ベース領域を形成する工
程と、全面に絶縁膜を堆積した後、前記開口部側壁に第
2の多結晶Si層を選択的に形成しこれをマスクとして
該開口部内の酸化膜をエッチング・除去して第2の開口
部を形成する工程と、前記第2の開口部内に形成した一
導電型多結晶5iJiJから一導電型不純物を基板内に
拡散させることによりエミッタ領域を形成するように構
成する。
[Detailed Description of the Invention] [Summary] An object of the present invention is to provide a method for manufacturing a bipolar transistor, in which an external base, an internal base, and an emitter are formed in a self-aligned manner with respect to a field oxide film. A step of selectively etching and removing a multilayer film formed on the substrate, consisting of a field oxide film, polycrystalline SiN of opposite conductivity type, and an insulating film to form an opening, and selectively etching a sidewall of the multilayer film of the opening. forming an external base region by diffusing an opposite conductivity type impurity into the substrate from the first opposite conductivity type polycrystalline Si layer formed in the first opposite conductivity type polycrystalline silicon layer; A step of implanting impurities of opposite conductivity type into the substrate using the polycrystalline Si layer as a mask to form an internal base region in contact with the external base region, and after depositing an insulating film on the entire surface, a second polycrystalline silicon layer is deposited on the side wall of the opening. A step of selectively forming a Si layer and using this as a mask to etch and remove the oxide film in the opening to form a second opening; An emitter region is formed by diffusing impurities of one conductivity type into the substrate.

〔産業上の利用分野] 本発明は半導体装置の製造方法に係り、特に自己整合に
よるバイポーラトランジスタの製造方法に関する。
[Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a bipolar transistor using self-alignment.

〔従来の技術〕[Conventional technology]

バイポーラトランジスタの高速化を図るためには、トラ
ンジスタの各部パターン寸法の微細化とともにパターン
間の位置ずれを小さくすることが必要であり、そのため
に自己整合法を用いたトランジスタの製造方法が提案・
実行されている。第2図(a)〜(d)は従来例を説明
するだめの工程断面図である。
In order to increase the speed of bipolar transistors, it is necessary to miniaturize the pattern dimensions of each part of the transistor and reduce the positional deviation between the patterns.
It is running. FIGS. 2(a) to 2(d) are process cross-sectional views for explaining a conventional example.

まず、同図(a)に示すようにn型Si基板21−、h
にフィールド酸化膜22を形成した後、全面に堆積した
p゛型多結晶Si層23及びCVD酸化膜24を通常の
フォトレジスト法を用いて選択的にエッチング・除去し
素子領域内に開口部を形成する。さらにp゛型多結晶S
i層23よりn型不純物を基板21内に拡散させて外部
ベース領域25を形成」−る。P゛型多結晶Si層23
はそのまま外部ベース領域25の引出し電極として機能
する。次いで同図0))に示すように該開口部内に熱酸
化膜25aを形成した後イオン注入法によりn型不純物
を該開口部に打ら込み内部ベース領域26を形成する。
First, as shown in FIG.
After forming a field oxide film 22, the p-type polycrystalline Si layer 23 and CVD oxide film 24 deposited on the entire surface are selectively etched and removed using a normal photoresist method to create an opening in the element region. Form. Furthermore, p type polycrystalline S
An n-type impurity is diffused into the substrate 21 from the i-layer 23 to form an external base region 25. P′ type polycrystalline Si layer 23
functions as an extraction electrode of the external base region 25 as it is. Next, as shown in FIG. 0), after a thermal oxide film 25a is formed in the opening, an n-type impurity is implanted into the opening by ion implantation to form an internal base region 26.

次いで同図(C)に示すようにCV’ D酸化膜27を
全面に堆積した後、該開り]部側壁のCVD酸化膜27
上に選択的にP゛型多結晶Si層28を形成する。次い
で同図(d)に示すように開口部側壁の多結晶Si層2
8をマスクとして核間「]部内の熱酸化膜25a及びC
VD酸化膜27をエッチンク電除去して窓開けし、さら
にこの上に形成したn゛型多結晶Sり層29からn型不
純物を拡散させてエミッタ領域30を形成する。
Next, as shown in FIG. 2C, after depositing a CV'D oxide film 27 on the entire surface, the CVD oxide film 27 on the side wall of the opening is deposited.
A P' type polycrystalline Si layer 28 is selectively formed thereon. Next, as shown in the same figure (d), the polycrystalline Si layer 2 on the side wall of the opening is
8 as a mask, the thermal oxide film 25a and C in the internuclear "] part
The VD oxide film 27 is removed by etching to form a window, and an emitter region 30 is formed by diffusing n-type impurities from the n-type polycrystalline S layer 29 formed thereon.

以上の工程によりエミッタ領域30を内部ベース領域2
6に対して自己整合的に形成することができる。
Through the above steps, the emitter region 30 is formed into the internal base region 2.
6 can be formed in a self-aligned manner.

(発明が解決しようとする課題) ところが上記の方法では外部ベース領域はフィールド酸
化膜に対して通常のマスク合わせによるバターニングに
よって形成され、自己整合的に形成されるものではない
。従ってマスク合わせの際の位置ずれを見込んで外部ベ
ース領域の幅を大きくすることが必要である。これはバ
イポーラトランジスタ全体の微細化を行う上で大きな妨
げとなるばかりでなく外部ベース幅のばらつきによるト
ランジスタ特性の不均一をもたらす。
(Problems to be Solved by the Invention) However, in the above method, the external base region is formed by patterning the field oxide film by normal mask alignment, and is not formed in a self-aligned manner. Therefore, it is necessary to increase the width of the external base region in consideration of positional deviation during mask alignment. This not only greatly hinders miniaturization of the entire bipolar transistor, but also causes non-uniformity in transistor characteristics due to variations in the external base width.

そこで本発明は、外部ベース、内部ベース及びエミッタ
をフィールド酸化膜に対して自己整合的に形成する方法
を提供し、以てバイポーラトランジスタの微細化及び特
性の均一化を図ることを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming an external base, an internal base, and an emitter in a self-aligned manner with respect to a field oxide film, thereby achieving miniaturization and uniformity of characteristics of bipolar transistors.

(課題を解決するだめの手段] 上記課題の解決は、一導電型基板−トに形成されたフィ
ールド酸化膜、反対導電型多結晶Si層及び絶縁膜から
なる多層膜を選択的にエッチング・除去して開口部を形
成する工程と、前記開口部の多層膜側壁に選択的に形成
した第1の反対導電型多結晶Si層から反対導電型不純
物を基板内に拡散させることにより外部ベース領域を形
成する工程と、前記開口部内に酸化膜を形成した後、前
記第1の多結晶5iJFJをマスクとして基板内に反対
導電型不純物を打ち込み前記外部ベース領域に接する内
部ベース領域を形成する工程と、全面に絶縁膜を堆積し
た後、前記開口部側壁に第2の多結晶Si層を選択的に
形成しこれをマスクとして該開口部内の酸化膜をエッチ
ング・除去して第2の開口部を形成する工程と、前記第
2の開口部内に形成した一導電型多結晶Si層から一導
電型不純物を基板内に拡散させることによりエミッタ領
域を形成する工程からなることを特徴とする半導体装置
の製造方法によって達成される。
(Means to Solve the Problem) The above problem can be solved by selectively etching and removing a multilayer film formed on a substrate of one conductivity type, consisting of a field oxide film, a polycrystalline Si layer of an opposite conductivity type, and an insulating film. forming an opening, and diffusing an opposite conductivity type impurity into the substrate from a first opposite conductivity type polycrystalline Si layer selectively formed on the sidewall of the multilayer film of the opening, thereby forming an external base region. forming an oxide film in the opening, and then implanting an opposite conductivity type impurity into the substrate using the first polycrystalline 5iJFJ as a mask to form an internal base region in contact with the external base region; After depositing an insulating film over the entire surface, a second polycrystalline Si layer is selectively formed on the side wall of the opening, and using this as a mask, the oxide film within the opening is etched and removed to form a second opening. and forming an emitter region by diffusing one conductivity type impurity into the substrate from the one conductivity type polycrystalline Si layer formed in the second opening. achieved by the method.

〔作 用〕[For production]

本発明の特徴は、フィールド酸化膜、反対導電型多結晶
Si層及び絶縁膜からなる多層膜を同一・マスクで同時
に選択エツチングして開口部を形成する点にある。この
ようにすることによって開口部側壁に形成した第1の多
結晶Si層を拡散源として形成される外部ベース領域は
素子分離用のフィールド酸化膜に対して自己整合的に形
成され、かつこの外部ベース領域の幅を第1の多結晶S
i層の膜厚で決まる極めて微細なものとすることが可能
となる。さらに外部ベース領域は何らの特別な工程を経
ることなく第1の多結晶Si層を介してフィールド酸化
膜上の反対導電型多結晶SR層に接続されて外部へ引き
出すことができる。内部ベース領域及びエミッタ領域は
以上のようにし、て形成された外部ベース領域に対して
自己整合的に形成され、それらの幅を極めて微細なもの
とづ−ることかできる。
A feature of the present invention is that openings are formed by selectively etching a multilayer film consisting of a field oxide film, a polycrystalline Si layer of opposite conductivity type, and an insulating film at the same time using the same mask. By doing this, the external base region formed using the first polycrystalline Si layer formed on the side wall of the opening as a diffusion source is formed in self-alignment with the field oxide film for element isolation, and this external base region is formed in a self-aligned manner with respect to the field oxide film for element isolation. The width of the base region is the first polycrystalline S
It becomes possible to make it extremely fine, which is determined by the thickness of the i-layer. Furthermore, the external base region can be connected to the polycrystalline SR layer of the opposite conductivity type on the field oxide film through the first polycrystalline Si layer and drawn out to the outside without going through any special process. As described above, the internal base region and the emitter region are formed in a self-aligned manner with respect to the formed external base region, and their widths can be made extremely fine.

〔実施例〕〔Example〕

第1図(a)〜(d)は本発明の実施例を示す工程断面
図である。
FIGS. 1(a) to 1(d) are process cross-sectional views showing an embodiment of the present invention.

同図(a)に示すように、最初にn型Si基板)」−に
通常の熱酸化法を用いて膜厚1μmのフィールド酸化膜
2を形成し、この上にボロン(B)をドープした膜70
.3μmのp“型多結晶5ii3、続いて膜厚0.5μ
mのCVD酸化膜4を形成する。次いでに記フィールド
酸化膜2、P゛型多結晶Si層31、CVD酸化膜4を
同時に選択エッチング・除去して幅0.8μmの開口部
を形成する。次いで、全面にボロンをドープした膜厚0
.3μmのp゛型多結晶Si層を成長させRUE法によ
り全面をエツチングして該開口部の側壁にのみp゛型多
結晶Si層5を残し熱処理すると、該p゛型多結晶Si
層5を拡散源として基板1内にボロンが拡散され外部ベ
ース領域6がフィールド酸化膜2に対して自己整合的に
形成される。次いで同図(b)に示すようにp゛型多結
晶Si層5及び開口部内の基板表面を酸化して、薄い酸
化膜7を形成する。さらにこの上にイオン注入決により
酸化膜7を通してボロンを打ち込んで内部ベース領域8
を形成する。次いで同図(C)に示すようにCVD酸化
膜9を全面に形成した後、前に述べた方法により開口部
側壁に多結晶34層10を形成し、これをマスクとして
開口部上の酸化膜7をエッチング・除去する。次いで同
図(d)に示すように多結晶Si層11を成長させ砒素
(As)を打ち込み熱処理してエミッタ領域12を内部
ベース領域8に対して自己整合的に形成する。なお、同
図(d)にみられるように、多結晶Si層3は開口部側
壁の多結晶Si層5を介して外部ベース領域6に接続さ
れ、ベース電橿として機能するものである。
As shown in Figure (a), first, a field oxide film 2 with a thickness of 1 μm was formed on an n-type Si substrate) using a normal thermal oxidation method, and boron (B) was doped thereon. membrane 70
.. 3 μm p” type polycrystalline 5ii3, followed by 0.5 μm film thickness
A CVD oxide film 4 having a thickness of m is formed. Next, the field oxide film 2, the P'-type polycrystalline Si layer 31, and the CVD oxide film 4 are selectively etched and removed simultaneously to form an opening with a width of 0.8 μm. Next, the entire surface is doped with boron and the film thickness is 0.
.. When a 3 μm p'-type polycrystalline Si layer is grown, the entire surface is etched by the RUE method, and the p'-type polycrystalline Si layer 5 is left only on the side wall of the opening, the p'-type polycrystalline Si layer 5 is heat-treated.
Boron is diffused into substrate 1 using layer 5 as a diffusion source, and external base region 6 is formed in self-alignment with field oxide film 2. Next, as shown in FIG. 2B, the p'-type polycrystalline Si layer 5 and the substrate surface within the opening are oxidized to form a thin oxide film 7. Furthermore, boron is implanted into the internal base region 8 through the oxide film 7 by ion implantation.
form. Next, as shown in FIG. 3(C), after forming a CVD oxide film 9 on the entire surface, a polycrystalline 34 layer 10 is formed on the side wall of the opening by the method described above, and using this as a mask, the oxide film on the opening is formed. 7 is etched and removed. Next, as shown in FIG. 2D, a polycrystalline Si layer 11 is grown, and arsenic (As) is implanted and heat treated to form an emitter region 12 in a self-aligned manner with respect to the internal base region 8. As shown in FIG. 2D, the polycrystalline Si layer 3 is connected to the external base region 6 via the polycrystalline Si layer 5 on the side wall of the opening, and functions as a base wire.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、フィールド酸化膜に対し
て外部ベース、内部ベース及びエミッタをマスクを用い
ることなく全て自己整合的に形成することができるため
、パターン寸法を微細化することができ、バイポーラト
ランジスタの高速化を図る上で極めて有益である。
As described above, according to the present invention, an external base, an internal base, and an emitter can be formed in a self-aligned manner without using a mask on a field oxide film, so that pattern dimensions can be miniaturized. , which is extremely useful in increasing the speed of bipolar transistors.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)は本発明の実施例を示す工程断面
図、 第2図(a)〜(d)は従来例の問題点を示す工程断面
図、 である。 図において、 l、21は一導電型基板、 2.22はフィールド酸化膜、 3.23は反対導電型多結晶Si層、 4.9.24.27は絶縁膜、 5は第1の反対導電型多結晶Si層、 6.25は外部ベース領域、 7は酸化膜、 8.26は内部ベース領域、 10は第2の反対導電型多結晶Si層、11.29は一
導電型多結晶Si層、 12.30はエミッタ領域、 25aは熱酸化膜、 28は多結晶Si層、 である。
FIGS. 1(a) to (d) are process cross-sectional views showing an embodiment of the present invention, and FIGS. 2(a) to (d) are process cross-sectional views showing problems in the conventional example. In the figure, 1, 21 is a substrate of one conductivity type, 2.22 is a field oxide film, 3.23 is a polycrystalline Si layer of an opposite conductivity type, 4.9, 24, 27 is an insulating film, and 5 is a first opposite conductivity type. type polycrystalline Si layer, 6.25 is an external base region, 7 is an oxide film, 8.26 is an internal base region, 10 is a second opposite conductivity type polycrystalline Si layer, 11.29 is one conductivity type polycrystalline Si layer 12.30 is an emitter region, 25a is a thermal oxide film, and 28 is a polycrystalline Si layer.

Claims (1)

【特許請求の範囲】 一導電型基板(1)上に形成されたフィールド酸化膜(
2)、反対導電型多結晶Si層(3)及び絶縁膜(4)
からなる多層膜を選択的にエッチング・除去して開口部
を形成する工程と、 前記開口部の多層膜側壁に選択的に形成した第1の反対
導電型多結晶Si層(5)から反対導電型不純物を基板
(1)内に拡散させることにより外部ベース領域(6)
を形成する工程と、 前記開口部内に酸化膜(7)を形成した後、前記第1の
多結晶Si層(5)をマスクとして基板(1)内に反対
導電型不純物を打ち込み、前記外部ベース領域(6)に
接する内部ベース領域(8)を形成する工程と、全面に
絶縁膜(9)を堆積した後、前記開口部側壁に第2の多
結晶Si層(10)を選択的に形成し、これをマスクと
して該開口部内の酸化膜(7)をエッチング・除去して
第2の開口部を形成する工程と、前記第2の開口部内に
形成した一導電型多結晶Si層(11)から一導電型不
純物を基板(1)内に拡散させることにより、エミッタ
領域(12)を形成する工程からなることを特徴とする
半導体装置の製造方法。
[Claims] A field oxide film (
2), opposite conductivity type polycrystalline Si layer (3) and insulating film (4)
forming an opening by selectively etching and removing a multilayer film made of External base region (6) by diffusing type impurities into the substrate (1)
After forming an oxide film (7) in the opening, impurities of opposite conductivity type are implanted into the substrate (1) using the first polycrystalline Si layer (5) as a mask to form the external base. After forming an internal base region (8) in contact with the region (6) and depositing an insulating film (9) on the entire surface, a second polycrystalline Si layer (10) is selectively formed on the side wall of the opening. Then, using this as a mask, the oxide film (7) in the opening is etched and removed to form a second opening, and the polycrystalline Si layer (11) of one conductivity type formed in the second opening is etched and removed. 1. A method for manufacturing a semiconductor device, comprising the step of forming an emitter region (12) by diffusing impurities of one conductivity type from ) into a substrate (1).
JP6421189A 1989-03-16 1989-03-16 Manufacture of semiconductor device Pending JPH02244636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6421189A JPH02244636A (en) 1989-03-16 1989-03-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6421189A JPH02244636A (en) 1989-03-16 1989-03-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02244636A true JPH02244636A (en) 1990-09-28

Family

ID=13251522

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6421189A Pending JPH02244636A (en) 1989-03-16 1989-03-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02244636A (en)

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