JPH01256123A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an impurity layer up to the deep part of a trench side surface, and increase the capacitance of a capacitor, by using an ion implantation mask having an aperture whose end-portion is formed in a tapered-type. CONSTITUTION:A resist mask 12 provided with an aperture having a taper angle theta1 is formed. After a trench 13 is formed by etching a P-type silicon substrate 11, arsenide ion 14 is implanted at an angle theta smaller than the angle theta1 with respect to the silicon substrate 11, and an impurity layer 15 is formed on the side wall of the trench. The resist mask 12 is eliminated, thermal oxidation is performed in an oxygen atmosphere, and a capacitor oxide film 16 is grown on the P-type silicon substrate and the surface of the trench 13. Successively polysilicon containing impurity is deposited on the capacitor oxide film 16, and turned into a capacitor electrode 17. Thereby the impurity layer 15 can be formed on the whole side surface of the trench, so that the capacitance of a capacitor can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a method for forming a trench capacitor.

[Conventional technology]

In a dynamic RAM having a memory cell composed of 1111 transistors and one capacitor, trench-type capacitors have been adopted due to higher integration. The capacitor is a silicon substrate.

It consists of a capacitor oxide film and a capacitor electrode, but when the capacitor electrode potential is set to half the power supply voltage, it is necessary to form an impurity layer on the silicon substrate in contact with the capacitor oxide film to create depletion.

A method of manufacturing a conventional trench capacitor in which an impurity layer is formed on the side surface of the trench is shown in FIGS. 3(a) and 3(b).

First, as shown in FIG. 3(a), a P-type silicon substrate 3
After forming a resist mask 32 having an opening at a predetermined position on the substrate 1, the P-type silicon substrate 31 is etched by RIE to form a groove 33. Subsequently, arsenic ions 34 are implanted into the side surface of the groove 33 to form an impurity layer 35. In this case, the ion implantation must be performed at an angle θ (usually 7°) that is not 0 degrees with respect to the silicon substrate 31 in order to form an impurity layer on the sides of the trench.

Next, as shown in FIG. 3(b), a resist mask 3 is applied.
2, a capacitor oxide film 36 is formed on the surfaces of the silicon substrate 31 and the groove 33 by thermal oxidation, and then polysilicon containing impurities is deposited by low pressure CVD to form a capacitor electrode 37.

[Problem to be solved by the invention]

In order to form an impurity layer on the side surface of the groove by ion implantation, it is necessary to perform ion implantation obliquely at an angle θ that is not 0 with respect to the silicon substrate. In this case, when the groove is deep, ions can reach the upper part of the inner side of the groove, forming an impurity layer, but at the lower part of the inner side of the groove, the resist above the upper part of the groove acts as a mask, and the ions cannot reach the lower part of the groove, forming an impurity layer. There is a drawback that the capacitance cannot be increased because there is a region in which the capacitance is not formed.

[Means to solve the problem]

In the method of manufacturing a semiconductor device of the present invention, after forming an ion implantation mask having a groove dug inward from the surface of a semiconductor substrate and an opening aligned with the groove and narrowing in width in the depth direction, ion implantation is performed. The method includes a step of forming an impurity layer on the side surface of the trench by an implantation method to form a trench capacitor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type silicon substrate 1
1. After patterning a resist film with a thickness of 1.5 μm so that openings are made at predetermined positions on one surface using the same method as before, and then post-baking at 120°C for about 1 hour, a taper of θ1 (approximately 30°) is created at the end. A resist mask 12 having angled openings is produced. Next, the P-type silicon substrate 11 is etched using the RIE method as in the conventional method.
After forming, the energy is 100 keV and the dose is 1×
When arsenic ions 14 of 1014/cI112 are implanted into the silicon substrate 11 at an angle θ (approximately 7°) smaller than θ1, an impurity layer 15 is formed on the trench side.

Next, as shown in FIG. 1(b), the resist mask 12
is removed and thermally oxidized in an oxygen atmosphere to form a P-type silicon substrate 1.
Capacitor oxide film 1 with a thickness of 10 nm on the surfaces of 1 and groove 13
Grow 6. Subsequently, polysilicon containing impurities is deposited on the capacitor oxide film 16 by a low pressure CVD method to form the capacitor electrode 17.

In this way, for example, the width and depth are each 1 μm.
The impurity layer 15 can be formed on the entire side surface of the 8 μm groove. Compared to the conventional example, which could only form to a depth of 6.6 μm, it is possible to form a capacitance of about 120%.

FIG. 2 is a cross-sectional view of a semiconductor chip for explaining the second embodiment. After a silicon oxide film 24 is deposited to a thickness of 400 nm on a P-type silicon substrate 21 by the CVD method, the resist film is buttered in a conventional manner so that openings are formed at predetermined positions. Next, when the silicon oxide film 22 is isotropically etched using the resist mask 22 formed in this way, the silicon oxide film 24 is etched by approximately
P-type silicon substrate 21 with a taper angle of 5°
Part of the surface is exposed. Subsequently, the P-type silicon substrate 21 is etched by RIE to form a groove 23. Thereafter, the resist mask 22 is removed, and using the silicon oxide film 24 as a mask for ion implantation, ion implantation is performed simultaneously with the first embodiment to form an impurity layer on the side surface of the trench, and the silicon oxide film 24 is removed to oxidize the capacitor. After forming the film and the capacitor electrode, a trench type capacitor similar to that shown in FIG. 1(b) is obtained.

In this case, since the taper angle utilizes side etching of the silicon oxide film 22, an ion implantation mask having a stable shape can be formed, and the impurity layer can be formed deeply with good reproducibility.

[Effects of the Invention] As explained above, when an impurity layer is formed on the side surface of a trench by oblique ion implantation, the present invention uses an ion implantation mask having an opening with a tapered end. Since the impurity layer can be formed deeply, the capacitance of the capacitor can be increased, and the thickness of the ion implantation mask can also be increased, which has the effect of improving the yield.

[Brief explanation of the drawing]

1(a) and 1(b) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining the first embodiment of the present invention;
The figure is a sectional view of a semiconductor chip for explaining a second embodiment, and FIGS. 3(a) and 3(b) are sectional views of semiconductor chips arranged in the order of steps for explaining a conventional example. 11.21.31...P-type silicon substrate, 12°22
．． 32...Resist mask, 13,23.33...
Groove, 14.34... Arsenic ion, 1.5.35...
Impurity layer, 16.36... Capacitor oxide film, 17°37... Capacitor electrode, 24... Silicon oxide film.

Claims (1)

[Claims] After forming an ion implantation mask having a groove dug inward from the surface of the semiconductor substrate and an opening aligned with the groove and narrowing in width in the depth direction, an impurity layer is formed on the sides of the groove by ion implantation. 1. A method of manufacturing a semiconductor device, comprising the step of forming a groove-type capacitor by providing a groove-type capacitor.