JP2680923B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2680923B2
JP2680923B2 JP27681790A JP27681790A JP2680923B2 JP 2680923 B2 JP2680923 B2 JP 2680923B2 JP 27681790 A JP27681790 A JP 27681790A JP 27681790 A JP27681790 A JP 27681790A JP 2680923 B2 JP2680923 B2 JP 2680923B2
Authority
JP
Japan
Prior art keywords
mask
oxide film
opening
trench
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP27681790A
Other languages
Japanese (ja)
Other versions
JPH04152549A (en
Inventor
光広 宮▲崎▼
Original Assignee
山口日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 山口日本電気株式会社 filed Critical 山口日本電気株式会社
Priority to JP27681790A priority Critical patent/JP2680923B2/en
Publication of JPH04152549A publication Critical patent/JPH04152549A/en
Application granted granted Critical
Publication of JP2680923B2 publication Critical patent/JP2680923B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Element Separation (AREA)
  • Weting (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にトレンチ
の形成方法に関する。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a trench.

〔従来の技術〕[Conventional technology]

従来の半導体基板へのトレンチの形成方法について第
2図を用いて説明する。
A conventional method of forming a trench in a semiconductor substrate will be described with reference to FIG.

まず、第2図(e)に示す様に、半導体基板1上の素
子分離領域にイオン注入によりチャネルストッパー5を
形成したのち厚い素子分離酸化膜4と、素子形成領域に
薄い酸化膜3を形成する。次いで全面にフォトレジスト
膜を形成したのちパターニングを行ない、素子分離酸化
膜4に接する開口部を有するマスク2を形成する。次
に、ウェット処理により半導体基板1上の薄い酸化膜3
をマスク2を用いてエッチングする。続いて、半導体基
板1をドライエッング法によりマスク2を用いてエッチ
ングしトレンチ6を形成する。この時、マスク2の開口
径L1とトレンチ6の上部の開口径L3はほぼ等しくなる。
First, as shown in FIG. 2 (e), a channel stopper 5 is formed in the element isolation region on the semiconductor substrate 1 by ion implantation, and then a thick element isolation oxide film 4 and a thin oxide film 3 are formed in the element formation region. To do. Next, a photoresist film is formed on the entire surface and then patterned to form a mask 2 having an opening in contact with the element isolation oxide film 4. Next, a thin oxide film 3 on the semiconductor substrate 1 is wet-processed.
Are etched using the mask 2. Then, the semiconductor substrate 1 is etched by the dry etching method using the mask 2 to form the trench 6. At this time, the opening diameter L 1 of the mask 2 and the opening diameter L 3 above the trench 6 become substantially equal.

次に、第2図(b)に示すように、マスク2を用いて
トレンチ6の側壁及び底部に、容量確保の為に半導体基
板1に対し、角度θでボロンをイオン注入し、ボロン拡
散層7を形成する。以下トレンチ表面に絶縁膜とポリシ
リコンからなる電極を形成し容量部を4完成させる。
Next, as shown in FIG. 2B, boron is ion-implanted into the side wall and the bottom of the trench 6 at an angle θ with respect to the semiconductor substrate 1 to secure the capacitance by using the mask 2 to form a boron diffusion layer. Form 7. Thereafter, an electrode made of an insulating film and polysilicon is formed on the surface of the trench to complete the capacitor section 4.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

上述した従来のトレンチの形成方法では次の問題を生
じる。
The conventional trench forming method described above has the following problems.

半導体基板上のフォトレジストの直下にある薄い酸化
膜3の開口径とトレンチの直径が殆ど同じである為に、
イオン注入によりトレンチ側壁及び底部にボロンイオン
を半導体基板に対し、斜め方向から打ち込む際、チャン
ネルストッパー5の拡散層にもボロンイオンが注入され
る。従って、トレンチ側壁のボロン拡散層の一部とチャ
ンネルストッバー5の一部がAの部分で重なり合い、ボ
ロン濃度が高くなる事により、トレンチ側壁からのリー
クパスが発生し、容量部で蓄積電荷量が小さくなり、半
導体装置の歩留りが悪化する。
Since the opening diameter of the thin oxide film 3 immediately below the photoresist on the semiconductor substrate and the diameter of the trench are almost the same,
When boron ions are implanted into the side wall and bottom of the trench into the semiconductor substrate from the oblique direction by ion implantation, the boron ions are also implanted into the diffusion layer of the channel stopper 5. Therefore, a portion of the boron diffusion layer on the side wall of the trench overlaps a portion of the channel stubber 5 at the portion A, and the boron concentration increases, so that a leak path from the side wall of the trench occurs and the amount of accumulated charge in the capacitor portion is increased. As a result, the yield of semiconductor devices deteriorates.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の半導体装置の製造方法は、半導体基板上の素
子形成領域上に薄い酸化膜をそして素子分離領域上にチ
ャネルストッパーを介して厚い素子分離酸化膜を形成す
る工程と、全面にフォトレジスト膜を形成したのちパタ
ーニングし素子形成領域上に前記素子分離酸化膜に接し
て第1の開口部を有する第1のマスクを形成する工程
と、この第1のマスクを用いウエットエッチング法によ
り前記薄い酸化膜をエッチングし第1の開口部より開口
径の小さい第2の開口部を有する第2のマスクを形成す
る工程と、この第2のマスクを用いドライエッチング法
により前記半導体基板をエッチングし第2のマスクより
開口径の大きいトレンチを形成する工程と、前記第1及
び第2のマスクを用い斜め上方より前記トレンチ表面に
ボロンをイオン注入する工程とを含んで構成される。
A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a thin oxide film on an element formation region on a semiconductor substrate and a thick element isolation oxide film on a device isolation region via a channel stopper, and a photoresist film on the entire surface. And then patterning to form a first mask having a first opening in contact with the element isolation oxide film on the element formation region, and using the first mask to wet etch the thin oxide film. A step of etching the film to form a second mask having a second opening having an opening diameter smaller than that of the first opening; and etching the semiconductor substrate by a dry etching method using the second mask Forming a trench having an opening diameter larger than that of the mask, and using the first and second masks, ion-implanting boron into the trench surface from obliquely above. Configured to include a step.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第1図(a),(b)は本発明の一実施例を説明する
ための半導体チップの断面図である。
1 (a) and 1 (b) are sectional views of a semiconductor chip for explaining one embodiment of the present invention.

まず第1図(a)に示すように、従来と同様の操作に
より半導体基板1に不純物をイオン注入してチャネルス
トッパー5を形成したのち、選択酸化法により素子形成
領域に薄い酸化膜3をそして素子分離領域に素子分離酸
化膜4を形成する。次で全面にフォトレジスト膜を形成
したのちパターニングし、素子分離酸化膜4に接する開
口径L1のマスク2Aを形成する。
First, as shown in FIG. 1 (a), impurities are ion-implanted into the semiconductor substrate 1 to form a channel stopper 5 by the same operation as in the prior art, and then a thin oxide film 3 is formed in the element formation region by a selective oxidation method. An element isolation oxide film 4 is formed in the element isolation region. Next, a photoresist film is formed on the entire surface and then patterned to form a mask 2A having an opening diameter L 1 in contact with the element isolation oxide film 4.

次に、このマスク2Aを用いてウェットエッチング処理
により半導体基板上の薄い酸化膜3をエッチングし、L1
より小さい開口径L2を有する開口部を形成する。次で、
この開口径L2を有する酸化膜をマスクとしドライエッチ
ング法により半導体基板1をパターニングし、開口径L2
より大きい開口径を有するトレンチとを形成する。この
際、ウェット処理時間及びバッファードフッ酸の処理液
を適切に選ぶ事により、マスク2Aの開口径L1と酸化膜3
の開口径L2の差を0.4μm程度にする。
Next, the thin oxide film 3 on the semiconductor substrate is etched by wet etching using this mask 2A, and L 1
An opening having a smaller opening diameter L 2 is formed. Next,
Using the oxide film having the opening diameter L 2 as a mask, the semiconductor substrate 1 is patterned by the dry etching method to form the opening diameter L 2
Forming a trench having a larger opening diameter. At this time, the opening diameter L 1 of the mask 2A and the oxide film 3 can be adjusted by appropriately selecting the wet processing time and the processing solution of buffered hydrofluoric acid.
The difference in the opening diameter L 2 is about 0.4 μm.

次に、第1図(b)に示すように、斜め上方よりイオ
ン注入によりボロンイオンを半導体基板1に対し角度θ
(10〜20度)でトレンチ6の側壁及び底部に打ち込み、
トレンチ6の側壁及び底部にボロン拡散層7を形成す
る。この時、薄い酸化膜3に形成された開口部の開口径
L2は、フォトレジストからなるマスク2Aの開口径L1より
小さいので、形成されたトレンチ6の側壁のボロン拡散
層7とチャネルストッパー5の拡散層は重なる事はな
い。従って従来のようにリークパスの発生がなくなるた
め、半導体装置の歩留りは向上する。
Next, as shown in FIG. 1B, boron ions are ion-implanted from obliquely above the semiconductor substrate 1 at an angle θ.
(10 to 20 degrees) drive into the sidewall and bottom of the trench 6,
A boron diffusion layer 7 is formed on the side wall and bottom of the trench 6. At this time, the opening diameter of the opening formed in the thin oxide film 3
Since L 2 is smaller than the opening diameter L 1 of the mask 2A made of photoresist, the boron diffusion layer 7 on the side wall of the formed trench 6 and the diffusion layer of the channel stopper 5 do not overlap each other. Therefore, unlike the conventional case, the generation of leak paths is eliminated, and the yield of semiconductor devices is improved.

すなわち第3図に示したように、フォトレジスト膜と
薄い酸化膜の開口径の差(L1−L2)がほとんど等しい場
合の歩留りは30〜40%であったのに対し本実施例の場合
は約90%の歩留りが得られた。
That is, as shown in FIG. 3, the yield was 30 to 40% when the difference in opening diameter (L 1 −L 2 ) between the photoresist film and the thin oxide film was almost the same, whereas the yield of the present embodiment was 30%. In this case, a yield of about 90% was obtained.

〔発明の効果〕〔The invention's effect〕

以上説明した様に本発明によれば、トレンチ側壁のボ
ロンの拡散層とチャネルストッパーの拡散層が重なり合
う事がなくなる為に、トレンチ側壁からチャンネルスト
ッパーへのリークパスが回避出来、半導体装置の歩留り
が向上するという効果がある。
As described above, according to the present invention, since the diffusion layer of boron on the side wall of the trench and the diffusion layer of the channel stopper do not overlap each other, a leak path from the side wall of the trench to the channel stopper can be avoided, and the yield of the semiconductor device is improved. There is an effect of doing.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a),(b)は本発明の一実施例を説明するた
めの半導体チップの断面図、第2図(a),(b)は従
来例を説明するための半導体チップの断面図、第3図は
開口径の差と歩留りとの関係を示す図である。 1……半導体基板、2,2A……マスク、3……薄い酸化
膜、4……素子分離酸化膜、5……チャネルストッパ
ー、6……トレンチ、7……ボロン拡散層。
1 (a) and 1 (b) are sectional views of a semiconductor chip for explaining an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are sectional views of a semiconductor chip for explaining a conventional example. FIG. 3 and FIG. 3 are views showing the relationship between the difference in aperture diameter and the yield. 1 ... Semiconductor substrate, 2, 2A ... Mask, 3 ... Thin oxide film, 4 ... Element isolation oxide film, 5 ... Channel stopper, 6 ... Trench, 7 ... Boron diffusion layer.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板上の素子形成領域上に薄い酸化
膜をそして素子分離領域上にチャネルストッパーを介し
て厚い素子分離酸化膜を形成する工程と、全面にフォト
レジスタ膜を形成したのちパターニングした素子形成領
域上に前記素子分離酸化膜に接して第1の開口部を有す
る第1のマスクを形成する工程と、この第1のマスクを
用いウエットエッチング法により前記薄い酸化膜をエッ
チングし第1の開口部より開口径の小さい第2の開口部
を有する第2のマスクを形成する工程と、この第2のマ
スクを用いドライエッチング法により前記半導体基板を
エッチングし第2のマスクより開口径の大きいトレンチ
を形成する工程と、前記第1及び第2のマスクを用い斜
め上方より前記トレンチ表面にボロンをイオン注入する
工程とを含むことを特徴とする半導体装置の製造方法。
1. A step of forming a thin oxide film on an element formation region on a semiconductor substrate and a thick element isolation oxide film on a device isolation region through a channel stopper, and a patterning after forming a photoresist film on the entire surface. Forming a first mask having a first opening in contact with the element isolation oxide film on the formed element formation region, and etching the thin oxide film by wet etching using the first mask. Forming a second mask having a second opening having a smaller opening diameter than the first opening; and etching the semiconductor substrate by a dry etching method using the second mask to form an opening having a diameter larger than that of the second mask. And forming a large trench, and ion-implanting boron into the trench surface obliquely from above using the first and second masks. The method of manufacturing a semiconductor device according to claim.
JP27681790A 1990-10-16 1990-10-16 Method for manufacturing semiconductor device Expired - Fee Related JP2680923B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27681790A JP2680923B2 (en) 1990-10-16 1990-10-16 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27681790A JP2680923B2 (en) 1990-10-16 1990-10-16 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH04152549A JPH04152549A (en) 1992-05-26
JP2680923B2 true JP2680923B2 (en) 1997-11-19

Family

ID=17574810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27681790A Expired - Fee Related JP2680923B2 (en) 1990-10-16 1990-10-16 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2680923B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69434736D1 (en) * 1993-08-31 2006-06-22 St Microelectronics Inc Isolation structure and method of manufacture
US5874346A (en) * 1996-05-23 1999-02-23 Advanced Micro Devices, Inc. Subtrench conductor formation with large tilt angle implant
US5767000A (en) * 1996-06-05 1998-06-16 Advanced Micro Devices, Inc. Method of manufacturing subfield conductive layer

Also Published As

Publication number Publication date
JPH04152549A (en) 1992-05-26

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