JPH03106755U - - Google Patents

Info

Publication number
JPH03106755U
JPH03106755U JP1990097377U JP9737790U JPH03106755U JP H03106755 U JPH03106755 U JP H03106755U JP 1990097377 U JP1990097377 U JP 1990097377U JP 9737790 U JP9737790 U JP 9737790U JP H03106755 U JPH03106755 U JP H03106755U
Authority
JP
Japan
Prior art keywords
semiconductor device
terminal piece
external
insulating substrate
lid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1990097377U
Other languages
English (en)
Other versions
JPH0749802Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990097377U priority Critical patent/JPH0749802Y2/ja
Priority to GB9119472A priority patent/GB2249869B/en
Priority to US07/760,906 priority patent/US5155660A/en
Priority to DE19914130899 priority patent/DE4130899C2/de
Publication of JPH03106755U publication Critical patent/JPH03106755U/ja
Application granted granted Critical
Publication of JPH0749802Y2 publication Critical patent/JPH0749802Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge

Landscapes

  • Multi-Conductor Connections (AREA)

Description

【図面の簡単な説明】
第１図ないし第３図は本考案の実施例１、第４
図、第５図は実施例２、第６図、第７図は従来例
の構造を示すものであり、第１図は半導体装置の
構成断面図、第２図ａ、第３図ａはそれぞれ第１
図における内部端子片の異なる具体例の構造図、
第２図ｂ、第３図ｂはそれぞれ第２図ａ、第３図
ａの矢視−，−断面図、第４図ａ、第５
図ａはそれぞれ異なるリード線の支持構造図、第
４図ｂ、第５図ｂはそれぞれ第４図ａ、第５図ａ
の矢視−，−断面図、第６図は半導体装
置の構成断面図、第７図は第６図における内部構
造の斜視図である。図において、 １……半導体素子、２……絶縁基板、２ａ……
回路パターン、４……放熱板、５……樹脂ケース
、５ａ……ケース蓋部、８……内部端子片、９…
…外部端子片、１０……端子支持座、１１……可
撓リード線（絶縁被覆電線）、１２……リード線
支持座。

Claims (1)

  1. 【実用新案登録請求の範囲】 １ 半導体素子、該半導体素子をマウントした絶
    縁基板、該絶縁基板の回路パターンに接続して引
    出した外部導出用端子を、放熱板と組合わせた樹
    脂ケース内に組み込んで構成した半導体装置にお
    いて、外部導出用端子を絶縁基板上に起立姿勢で
    半田付けした内部端子片と、樹脂ケースの蓋部に
    貫通装着した外部端子片とに分割し、かつ内部端
    子片の上端を前記蓋部の内面側に形成した端子片
    支持座へ差し込み式に保持するとともに、内部端
    子片と外部端子片との間を可撓リード線で相互接
    続したことを特徴とする半導体装置。 ２ 半導体素子、該半導体素子をマウントした絶
    縁基板、該絶縁基板の回路パターンに接続して引
    出した外部導出用端子を、放熱板と組合わせた樹
    脂ケース内に組み込んで構成した半導体装置にお
    いて、外部導出用端子を絶縁基板上に起立姿勢で
    半田付けした内部端子片と、樹脂ケースの蓋部に
    貫通装着した外部端子片とに分割し、かつ内部端
    子片の上端を前記蓋部の内面側に形成した端子片
    支持座へ差し込み式に保持した上で、該内部端子
    片と外部端子片との間を可撓リード線で相互接続
    するとともに、該可撓リード線の途中箇所を前記
    蓋部の内面側に形成したリード線支持座に保持し
    たことを特徴とする半導体装置。 ３ 請求項１，２のいずれかに記載の半導体装置
    において、可撓リード線が絶縁被覆電線であるこ
    とを特徴とする半導体装置。 ４ 請求項１，２のいずれかに記載の半導体装置
    において、半導体素子が少なくともダイオード、
    サイリスタ、トランジスタのいずれかであること
    を特徴とする半導体装置。
JP1990097377U 1989-12-28 1990-09-17 半導体装置 Expired - Lifetime JPH0749802Y2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP1990097377U JPH0749802Y2 (ja) 1989-12-28 1990-09-17 半導体装置
GB9119472A GB2249869B (en) 1990-09-17 1991-09-12 Semiconductor device
US07/760,906 US5155660A (en) 1990-09-17 1991-09-17 Semiconductor device
DE19914130899 DE4130899C2 (de) 1990-09-17 1991-09-17 Halbleitervorrichtung

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP15258989 1989-12-28
JP1-152589 1989-12-28
JP1990097377U JPH0749802Y2 (ja) 1989-12-28 1990-09-17 半導体装置

Publications (2)

Publication Number Publication Date
JPH03106755U true JPH03106755U (ja) 1991-11-05
JPH0749802Y2 JPH0749802Y2 (ja) 1995-11-13

Family

ID=31718719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990097377U Expired - Lifetime JPH0749802Y2 (ja) 1989-12-28 1990-09-17 半導体装置

Country Status (1)

Country Link
JP (1) JPH0749802Y2 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011054896A (ja) * 2009-09-04 2011-03-17 Nippon Inter Electronics Corp パワー半導体モジュール
JP2013065836A (ja) * 2011-08-31 2013-04-11 Mitsubishi Electric Corp 電極部材およびこれを用いた電力用半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3085655U (ja) * 2001-09-17 2002-05-17 一三 木村 立体組み合わせパズル

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3085655U (ja) * 2001-09-17 2002-05-17 一三 木村 立体組み合わせパズル

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011054896A (ja) * 2009-09-04 2011-03-17 Nippon Inter Electronics Corp パワー半導体モジュール
JP2013065836A (ja) * 2011-08-31 2013-04-11 Mitsubishi Electric Corp 電極部材およびこれを用いた電力用半導体装置

Also Published As

Publication number Publication date
JPH0749802Y2 (ja) 1995-11-13

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