JPH03122536U - - Google Patents

Info

Publication number
JPH03122536U
JPH03122536U JP1990031768U JP3176890U JPH03122536U JP H03122536 U JPH03122536 U JP H03122536U JP 1990031768 U JP1990031768 U JP 1990031768U JP 3176890 U JP3176890 U JP 3176890U JP H03122536 U JPH03122536 U JP H03122536U
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor
edge
circuit device
small protrusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990031768U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990031768U priority Critical patent/JPH03122536U/ja
Publication of JPH03122536U publication Critical patent/JPH03122536U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第1図は本考案に係る半導体実装回路装置の要
部構成例を示す断面図、第2図は本考案に係る半
導体実装回路装置の構成に使用する半導体素子の
斜視図、第3図は本考案に係る半導体実装回路装
置の他の要部構成例を示す断面図、第4図は従来
の半導体実装回路装置の要部構成を示す断面図で
ある。 1,1a…半導体素子、2,2a…半導体素子
の端縁部、3,3a…ボンデイングワイヤ、4,
4a…回路基板、5,5a…接続用パツド、6,
6a…半導体素子のボンデイングパツド、7,7
′…絶縁体からなる小突条。

Claims (1)

  1. 【実用新案登録請求の範囲】 内部または表面に導体回路パターンが形成され
    た回路基板の表面所定位置に、半導体素子をワイ
    ヤボンデイングによつて実装して成る半導体実装
    回路装置において、 前記半導体素子の端縁部近傍に、絶縁体からな
    る小突条を周設し、前記小突条によつて前記半導
    体素子と前記導体回路パターンとを接続するボン
    デイングワイヤが半導体素子の端縁部を越えるよ
    うに担持されて成ることを特徴とする半導体実装
    回路装置。
JP1990031768U 1990-03-27 1990-03-27 Pending JPH03122536U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990031768U JPH03122536U (ja) 1990-03-27 1990-03-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990031768U JPH03122536U (ja) 1990-03-27 1990-03-27

Publications (1)

Publication Number Publication Date
JPH03122536U true JPH03122536U (ja) 1991-12-13

Family

ID=31534560

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990031768U Pending JPH03122536U (ja) 1990-03-27 1990-03-27

Country Status (1)

Country Link
JP (1) JPH03122536U (ja)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56158440A (en) * 1980-05-12 1981-12-07 Hitachi Ltd Semiconductor device
JPH0254567A (ja) * 1988-08-17 1990-02-23 Nec Kyushu Ltd 樹脂封止型半導体装置
JPH02166743A (ja) * 1988-12-21 1990-06-27 Nec Corp 半導体集積回路装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56158440A (en) * 1980-05-12 1981-12-07 Hitachi Ltd Semiconductor device
JPH0254567A (ja) * 1988-08-17 1990-02-23 Nec Kyushu Ltd 樹脂封止型半導体装置
JPH02166743A (ja) * 1988-12-21 1990-06-27 Nec Corp 半導体集積回路装置

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