JPH0292955U - - Google Patents
Info
- Publication number
- JPH0292955U JPH0292955U JP1989001018U JP101889U JPH0292955U JP H0292955 U JPH0292955 U JP H0292955U JP 1989001018 U JP1989001018 U JP 1989001018U JP 101889 U JP101889 U JP 101889U JP H0292955 U JPH0292955 U JP H0292955U
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- led chip
- reflector
- display element
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
Description
第１図は本考案実施例の正面構造を示す図、第
２図は本考案実施例の側面構造を示す図、第３図
は本考案実施例の上面構造を示す図、第４図は本
考案実施例のリードフレームの正面構造を示す図
、第５図は本考案実施例のリードフレームの側面
構造を示す図、第６図は本考案実施例の製造方法
を説明する図、第７図は従来例の斜視構造を示す
図、第８図と第９図は従来例の製造方法を説明す
る図である。
１……反射器、２，３，４……リードフレーム
、５……ＬＥＤチツプ、６……金線、７……透明
樹脂。
Fig. 1 is a diagram showing the front structure of the embodiment of the invention, Fig. 2 is a diagram showing the side structure of the embodiment of the invention, Fig. 3 is a diagram showing the top structure of the embodiment of the invention, and Fig. 4 is a diagram showing the structure of the embodiment of the invention. FIG. 5 is a diagram showing the front structure of the lead frame according to the embodiment of the invention. FIG. 6 is a diagram illustrating the manufacturing method of the embodiment of the invention. FIG. 1 is a diagram showing a perspective structure of a conventional example, and FIGS. 8 and 9 are diagrams for explaining a manufacturing method of a conventional example. 1... Reflector, 2, 3, 4... Lead frame, 5... LED chip, 6... Gold wire, 7... Transparent resin.
Claims (1)
射器、ＬＥＤチツプ及びＬＥＤチツプへの給電端
子であるリードフレームが透明樹脂によりモール
ドされた構造のＬＥＤ表示素子において、上記反
射器はカツプ状の反射面及びリードフレームの端
部が嵌合する孔を有し、上記孔に嵌合したリード
フレームが反射面の底に露出し、この反射面の底
のリードフレームの上にＬＥＤチツプが搭載され
た構造であることを特徴とするＬＥＤ表示素子。 In an LED display element, an LED chip is mounted on the bottom of the reflector, and the reflector, the LED chip, and a lead frame serving as a power supply terminal for the LED chip are molded with transparent resin. It has a hole into which the surface and the end of the lead frame fit, the lead frame fitted into the hole is exposed at the bottom of the reflective surface, and an LED chip is mounted on the lead frame at the bottom of the reflective surface. An LED display element characterized by a structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989001018U JPH0525257Y2 (en) | 1989-01-09 | 1989-01-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989001018U JPH0525257Y2 (en) | 1989-01-09 | 1989-01-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0292955U true JPH0292955U (en) | 1990-07-24 |
| JPH0525257Y2 JPH0525257Y2 (en) | 1993-06-25 |
Family
ID=31200539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989001018U Expired - Lifetime JPH0525257Y2 (en) | 1989-01-09 | 1989-01-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0525257Y2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005101661A (en) * | 2004-12-24 | 2005-04-14 | Sanyo Electric Co Ltd | Light emitting diode lamp |
| JP2005101662A (en) * | 2004-12-24 | 2005-04-14 | Sanyo Electric Co Ltd | Light emitting diode lamp |
| JP4703903B2 (en) * | 2001-07-17 | 2011-06-15 | ローム株式会社 | Semiconductor device manufacturing method and semiconductor device |
-
1989
- 1989-01-09 JP JP1989001018U patent/JPH0525257Y2/ja not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4703903B2 (en) * | 2001-07-17 | 2011-06-15 | ローム株式会社 | Semiconductor device manufacturing method and semiconductor device |
| JP2005101661A (en) * | 2004-12-24 | 2005-04-14 | Sanyo Electric Co Ltd | Light emitting diode lamp |
| JP2005101662A (en) * | 2004-12-24 | 2005-04-14 | Sanyo Electric Co Ltd | Light emitting diode lamp |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0525257Y2 (en) | 1993-06-25 |