JPH028327B2 - - Google Patents

Info

Publication number
JPH028327B2
JPH028327B2 JP55118218A JP11821880A JPH028327B2 JP H028327 B2 JPH028327 B2 JP H028327B2 JP 55118218 A JP55118218 A JP 55118218A JP 11821880 A JP11821880 A JP 11821880A JP H028327 B2 JPH028327 B2 JP H028327B2
Authority
JP
Japan
Prior art keywords
operand
byte
bytes
address
unnecessary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP55118218A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5743239A (en
Inventor
Tomoatsu Yanagida
Motonori Nagafuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55118218A priority Critical patent/JPS5743239A/ja
Priority to KR1019810002548A priority patent/KR860000791B1/ko
Priority to US06/294,053 priority patent/US4456955A/en
Publication of JPS5743239A publication Critical patent/JPS5743239A/ja
Publication of JPH028327B2 publication Critical patent/JPH028327B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49936—Normalisation mentioned as feature only

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
JP55118218A 1980-08-27 1980-08-27 Data processor Granted JPS5743239A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP55118218A JPS5743239A (en) 1980-08-27 1980-08-27 Data processor
KR1019810002548A KR860000791B1 (ko) 1980-08-27 1981-07-14 데이터처리장치
US06/294,053 US4456955A (en) 1980-08-27 1981-08-18 Alignment of one operand of a two operand arithmetic unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55118218A JPS5743239A (en) 1980-08-27 1980-08-27 Data processor

Publications (2)

Publication Number Publication Date
JPS5743239A JPS5743239A (en) 1982-03-11
JPH028327B2 true JPH028327B2 (show.php) 1990-02-23

Family

ID=14731136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55118218A Granted JPS5743239A (en) 1980-08-27 1980-08-27 Data processor

Country Status (3)

Country Link
US (1) US4456955A (show.php)
JP (1) JPS5743239A (show.php)
KR (1) KR860000791B1 (show.php)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0827716B2 (ja) * 1985-10-25 1996-03-21 株式会社日立製作所 データ処理装置及びデータ処理方法
JP2504847B2 (ja) * 1989-10-27 1996-06-05 甲府日本電気株式会社 １０進デ―タのチェック回路
US5168571A (en) * 1990-01-24 1992-12-01 International Business Machines Corporation System for aligning bytes of variable multi-bytes length operand based on alu byte length and a number of unprocessed byte data
CA2045705A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites In-register data manipulation in reduced instruction set processor
JPH04116717A (ja) * 1990-09-07 1992-04-17 Koufu Nippon Denki Kk オーバーフロー例外検出方式
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
US6735685B1 (en) * 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
WO1994008287A1 (en) 1992-09-29 1994-04-14 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
EP0593073A1 (en) * 1992-10-16 1994-04-20 Matsushita Electric Industrial Co., Ltd. A processor incorporating shifters
US5463746A (en) * 1992-10-30 1995-10-31 International Business Machines Corp. Data processing system having prediction by using an embedded guess bit of remapped and compressed opcodes
US6219773B1 (en) * 1993-10-18 2001-04-17 Via-Cyrix, Inc. System and method of retiring misaligned write operands from a write buffer
US5615402A (en) * 1993-10-18 1997-03-25 Cyrix Corporation Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch
US5584009A (en) * 1993-10-18 1996-12-10 Cyrix Corporation System and method of retiring store data from a write buffer
US5740398A (en) * 1993-10-18 1998-04-14 Cyrix Corporation Program order sequencing of data in a microprocessor with write buffer
US5471598A (en) * 1993-10-18 1995-11-28 Cyrix Corporation Data dependency detection and handling in a microprocessor with write buffer
US5673216A (en) * 1995-12-19 1997-09-30 International Business Machines Corporation Process and system for adding or subtracting symbols in any base without converting to a common base
US6557096B1 (en) * 1999-10-25 2003-04-29 Intel Corporation Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types
US6732203B2 (en) * 2000-01-31 2004-05-04 Intel Corporation Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus
JP3845814B2 (ja) * 2000-08-10 2006-11-15 株式会社テルミナス・テクノロジー 連想メモリとその検索方法及びルータとネットワークシステム
US7716267B2 (en) * 2004-08-30 2010-05-11 Casio Computer Co., Ltd. Decimal computing apparatus, electronic device connectable decimal computing apparatus, arithmetic operation apparatus, arithmetic operation control apparatus, and program-recorded recording medium
US10459731B2 (en) * 2015-07-20 2019-10-29 Qualcomm Incorporated Sliding window operation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4135242A (en) * 1977-11-07 1979-01-16 Ncr Corporation Method and processor having bit-addressable scratch pad memory
US4189768A (en) * 1978-03-16 1980-02-19 International Business Machines Corporation Operand fetch control improvement
US4219874A (en) * 1978-03-17 1980-08-26 Gusev Valery Data processing device for variable length multibyte data fields
US4268909A (en) * 1979-01-02 1981-05-19 Honeywell Information Systems Inc. Numeric data fetch - alignment of data including scale factor difference
JPS6041768B2 (ja) * 1979-01-19 1985-09-18 株式会社日立製作所 デ−タ処理装置

Also Published As

Publication number Publication date
KR830006739A (ko) 1983-10-06
JPS5743239A (en) 1982-03-11
KR860000791B1 (ko) 1986-06-25
US4456955A (en) 1984-06-26

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