JPH0278295A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH0278295A JPH0278295A JP23040888A JP23040888A JPH0278295A JP H0278295 A JPH0278295 A JP H0278295A JP 23040888 A JP23040888 A JP 23040888A JP 23040888 A JP23040888 A JP 23040888A JP H0278295 A JPH0278295 A JP H0278295A
- Authority
- JP
- Japan
- Prior art keywords
- solder resist
- board
- conductor circuit
- resist
- photo solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910000679 solder Inorganic materials 0.000 claims abstract description 35
- 239000004020 conductor Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000011282 treatment Methods 0.000 abstract description 3
- 238000001035 drying Methods 0.000 abstract description 2
- 238000006116 polymerization reaction Methods 0.000 abstract description 2
- 230000001678 irradiating effect Effects 0.000 abstract 2
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000001723 curing Methods 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- SCYULBFZEHDVBN-UHFFFAOYSA-N 1,1-Dichloroethane Chemical compound CC(Cl)Cl SCYULBFZEHDVBN-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000035479 physiological effects, processes and functions Effects 0.000 description 1
- 238000010019 resist printing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、電子機器等に使用されるプリント配線板の製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing printed wiring boards used in electronic devices and the like.
従来の技術
従来の高密度のツーリント配線板のソルダレジストの製
造方法は第２図に示すようなフォト法による形成であっ
た。つ１す、基板１上に導体２の回路を形成し、その上
に、フォトレジスト３を塗布し、溶剤の一部を除去し乾
燥被膜を形成する（第２図ａ）。次に、マスクフィルム
６を密着させ紫外線４を露光した後（第２図ｂ）、所定
の現像液で未露光部分を溶解除去する（第２図Ｃ）６そ
して、残分の露光部の溶剤除去及び重合硬化のため熱硬
化を行う。2. Description of the Related Art The conventional method for manufacturing a solder resist for a high-density tooling wiring board was a photo method as shown in FIG. First, a circuit of conductors 2 is formed on a substrate 1, a photoresist 3 is applied thereon, and a part of the solvent is removed to form a dry film (FIG. 2a). Next, after the mask film 6 is tightly attached and exposed to ultraviolet rays (Fig. 2b), the unexposed areas are dissolved and removed using a prescribed developer (Fig. 2C). Heat curing is performed for removal and polymerization curing.
発明が解決しようとする課題
このようなプリント配線板の製造方法においては、露光
の際、マスクフィルムらと基板１との位置合わせが通常
片側０．０６〜０．１ ｍｍと極めて高い精度を要する
工程であり、また、元の回り込み及び解像性向上のため
、マスクフィルム６と基板１とを密着させるのＫ、一般
には真空吸着を用いており、露光部のセツティングに３
０〜θＯ秒、真空密着に１０〜２０秒、露光に２０〜４
０秒の時間を要し、生産性を著しく悪くするものであっ
た。Problems to be Solved by the Invention In this method of manufacturing a printed wiring board, during exposure, extremely high precision is required for alignment between the mask film and the substrate 1, usually 0.06 to 0.1 mm on one side. In addition, in order to improve the original wrapping and resolution, vacuum suction is generally used to bring the mask film 6 and substrate 1 into close contact, and three steps are taken to set the exposed area.
0 to θO seconds, 10 to 20 seconds for vacuum contact, 20 to 4 seconds for exposure
This took 0 seconds and significantly reduced productivity.
本発明は、これらの課題を解決するため、露光の際、マ
スクフィルムを必要とせず、マスクフィルムと基板の位
置合わせ及び、真空吸着全省略することによって、生産
性、精度を飛躍的に向上させることを目的としたもので
ある。In order to solve these problems, the present invention dramatically improves productivity and accuracy by eliminating the need for a mask film during exposure, and completely omitting alignment of the mask film and substrate and vacuum suction. It is intended for this purpose.
課題を解決するだめの手段
この課題を解決するだめに本発明は、絶縁基板に形成さ
れた回路面側にフォトソルダレジストを前記回路を含む
一部又は全面に形成し、その形成面の絶縁基板を介した
反対面から、露光をすることにより、前記フォトソルダ
レジストを硬化させ、その後、心体回路上の遮光された
未露光のフォトソルダレジストを現像・除去することを
特徴とするものである。Means for Solving the Problem In order to solve this problem, the present invention forms a photo solder resist on a part or the entire surface including the circuit on the side of the circuit formed on the insulating substrate, and then removes the photo solder resist from the insulating substrate on the surface where the photo solder resist is formed. The method is characterized in that the photo solder resist is cured by exposing it to light from the opposite side through the substrate, and then the unexposed photo solder resist that is shielded from light on the core circuit is developed and removed. .
作用
この製造方法によれば、フォトソルダレジスト塗布而の
導体回路がマスクフィルムの晟光部の役目をなし、導体
回路のない部分のフォトツルタレシストを硬化させマス
クフィルムを用いず、しかも真空吸着、位置合わせ、も
することなく、高速で。Function: According to this manufacturing method, the conductor circuit coated with the photo solder resist serves as a lightening part of the mask film, and the photo solder resist in the area where there is no conductor circuit is hardened, and a mask film is not used, and vacuum suction is not required. , at high speed without alignment.
高精度なソルダレジストを形成することができる。っ実
施例
以下、本発明の実施例を第１図ａ ｒｙ ｄの添付図面
にもとづいて説明する。A highly accurate solder resist can be formed. Embodiments Hereinafter, embodiments of the present invention will be described based on the accompanying drawings of FIG.
３６５ｎｍの波長の紫外線透過率がａｏ％〜５０チで一
定の厚みを保ったガラス−エポキシからなる絶縁基板１
１上に導体回路１２を形成する。An insulating substrate 1 made of glass-epoxy with a constant thickness and an ultraviolet transmittance of 365 nm wavelength from ao% to 50 cm.
A conductive circuit 12 is formed on the conductor circuit 1.
その絶縁基板１１の回路形成面側に適正露光量６ｏ○〜
６０ｏｍＪ／Ｃ１１（塗膜厚：２０〜３０μｍ）で、し
かも、３６５ｎｍの感光波長ピークを有するフォトソル
ダレジスト１３を塗布し、仮乾燥等の所定の処理を行う
（第１図ａ〕。その後、塗布面の反対面から、１００ｏ
〜１６ｏＱｍＪ／Ｃ４の露光量で、３６５ｎｍの波長を
有する紫外線１４を用いて露光し、絶縁基板１１を透過
して、フォトソルダレジスト１３を光重合により硬化さ
せる（第１図ｂ）。次に、硬化後の絶縁基板１１を所定
の現像液（変性１−１−１）リクロロエタン）を有する
現像槽にて、１．５〜２．５ｋｑ１０ｎのスプレー圧力
で３０〜θ○秒の条件で現像すると、導体回路１２上の
７オトソルダレジスト１３は導体回路１２に遮光されて
未硬化となるため、現像にて溶解、除去され、第１図Ｃ
に示したようなソルダレジスト１３のパターンを形成す
ることができる。Appropriate exposure amount 6 o○ ~ on the circuit forming surface side of the insulating substrate 11
A photo solder resist 13 having a photosensitive wavelength peak of 365 nm is coated at 60 omJ/C11 (coating thickness: 20 to 30 μm), and predetermined treatments such as temporary drying are performed (Fig. 1 a). From the opposite side of the surface, 100o
Exposure is performed using ultraviolet rays 14 having a wavelength of 365 nm at an exposure dose of ~16 oQmJ/C4, which passes through the insulating substrate 11 and hardens the photosolder resist 13 by photopolymerization (FIG. 1b). Next, the cured insulating substrate 11 is heated in a developer tank containing a predetermined developer (modified 1-1-1) dichloroethane under conditions of 30 to θ○ seconds at a spray pressure of 1.5 to 2.5 kq10n. When developed, the solder resist 13 on the conductor circuit 12 is shielded from light by the conductor circuit 12 and becomes uncured, so it is dissolved and removed by the development, and as shown in FIG.
It is possible to form a pattern of the solder resist 13 as shown in FIG.
そして、転出した導体回路１２を被覆するため、スクリ
ーン印刷法を用いて、第１図ｄに示したような、ｐ−硬
化型ソルダレジスト１５を形成し、フォトソルダレジス
ト１３とともに熱硬化を行う。Then, in order to cover the transferred conductor circuit 12, a p-curing type solder resist 15 as shown in FIG.
熱硬化型ソルダレジスト１５の形成においては、本発明
のフォトソルダレジスト１３によって、高密度部分の形
成が終了しているため、スクリーンと絶縁基板１１め合
致り度は、片側ｏ：１６〜０．２５ｔｒａｎ稈度となり
、一般のソルダレジストの印刷条件で容易に形成するこ
とができる。In the formation of the thermosetting solder resist 15, since the formation of the high-density portion has been completed using the photo solder resist 13 of the present invention, the degree of matching between the screen and the insulating substrate 11 is one side o: 16 to 0. It has a culm of 25 tran and can be easily formed under general solder resist printing conditions.
なお、本発明に使用するフォトソルダレジスト１３は、
従来のものよりも胸元感度を高くしたものを用いること
が望ましく、また、絶縁基板１１の紫外線透過率を高く
することによって一層生産性の向上を図ることができる
。さらに、熱硬化型ソルダレジスト１５は、スクリーン
印刷法の紫外線硬化型ソルダレジストにおきかえること
もできる。Note that the photo solder resist 13 used in the present invention is
It is desirable to use a device with higher chest sensitivity than the conventional one, and by increasing the ultraviolet transmittance of the insulating substrate 11, productivity can be further improved. Furthermore, the thermosetting solder resist 15 can be replaced with an ultraviolet curable solder resist using screen printing.
発明の効果
以上のように、本発明によれば、従来のフォト法による
プリント配線板のソルダレジストの形成で、マスクフィ
ルムや絶縁基板との位置合わせを必要とせず、また接触
露光型における真空吸着も必要としないことから、生理
性は２倍以上向上させることができる。さらに、導体回
路が露光の際の遮光部を形成していることから、導体回
路とソルダレジストの合わせズレは皆無となり、極めて
精度の高いソルダレジストを容易に形成することができ
る。Effects of the Invention As described above, according to the present invention, it is possible to form a solder resist for a printed wiring board using the conventional photo method without requiring alignment with a mask film or an insulating substrate, and with vacuum suction in a contact exposure type. Physiology can be improved by more than twice since it is not necessary. Furthermore, since the conductor circuit forms a light-shielding portion during exposure, there is no misalignment between the conductor circuit and the solder resist, making it possible to easily form a solder resist with extremely high precision.
第１図ａ ％ ｄは、本発明の一実施例におけるプリン
ト配線板の製造方法を示す断面図、第２図ａ〜Ｃは、従
来のプリント配線板の製造方法を示す断面図である。
１１・・・・・・入射光が透過可能な基板、１２・川・
・導体回路、１３・・・・・・フォトソルダレジスト、
１４・・・・・・紫外光、１５・川・・熱硬化型ソルダ
レジスト。
代理人の氏名 弁理士 粟 野 重 孝 ほか１名第
１！ｇ
ノ３フォトソルダνシタト
＼
ゝ１１．ＮＪｔｃＸ攻
／４東゛グオ町
第２図
？ ３
Ａ ／’1A to 1D are cross-sectional views showing a method for manufacturing a printed wiring board according to an embodiment of the present invention, and FIGS. 2A to 2C are cross-sectional views showing a conventional method for manufacturing a printed wiring board. 11...Substrate through which incident light can pass, 12. River.
・Conductor circuit, 13...Photo solder resist,
14...Ultraviolet light, 15...Thermosetting solder resist. Name of agent: Patent attorney Shigetaka Awano and 1 other person
1! G ノ3 Photo solder ν Shitato ＼ ゝ11. NJtcX Attack/4 Higashiguo Town Figure 2? 3 A/'
Claims (1)
ジストを前記導体回路を含む一部又は全面に形成し、そ
の形成面の絶縁基板を介した反対面から、露光をするこ
とによサ、前記フォトソルダレジストを硬化させ、その
後、導体回路上の遮光された未露光のフォトソルダレジ
ストを現像・除去することを特徴とするプリント配線板
の製造方法。By forming a photo solder resist on a part or the entire surface including the conductor circuit on the side of the conductor circuit formed on the insulating substrate, and exposing it to light from the opposite side of the formed side with the insulating substrate interposed therebetween, A method for producing a printed wiring board, which comprises curing a photo solder resist, and then developing and removing the light-shielded, unexposed photo solder resist on a conductor circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63230408A JP2802079B2 (en) | 1988-09-14 | 1988-09-14 | Manufacturing method of printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63230408A JP2802079B2 (en) | 1988-09-14 | 1988-09-14 | Manufacturing method of printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0278295A true JPH0278295A (en) | 1990-03-19 |
| JP2802079B2 JP2802079B2 (en) | 1998-09-21 |
Family
ID=16907419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63230408A Expired - Fee Related JP2802079B2 (en) | 1988-09-14 | 1988-09-14 | Manufacturing method of printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2802079B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02252287A (en) * | 1989-03-27 | 1990-10-11 | Tamura Kaken Kk | Formation of solder mask for printed-wiring board |
| JPH0738236A (en) * | 1993-07-19 | 1995-02-07 | Hitachi Aic Inc | Manufacture of printed wiring board |
| CN106028669A (en) * | 2016-07-13 | 2016-10-12 | 广德新三联电子有限公司 | Novel circuit board solder mask PIN alignment method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS583399A (en) * | 1981-06-29 | 1983-01-10 | Toshiba Corp | Manufacture for piezoelectric oscillator |
-
1988
- 1988-09-14 JP JP63230408A patent/JP2802079B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS583399A (en) * | 1981-06-29 | 1983-01-10 | Toshiba Corp | Manufacture for piezoelectric oscillator |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02252287A (en) * | 1989-03-27 | 1990-10-11 | Tamura Kaken Kk | Formation of solder mask for printed-wiring board |
| JPH0738236A (en) * | 1993-07-19 | 1995-02-07 | Hitachi Aic Inc | Manufacture of printed wiring board |
| CN106028669A (en) * | 2016-07-13 | 2016-10-12 | 广德新三联电子有限公司 | Novel circuit board solder mask PIN alignment method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2802079B2 (en) | 1998-09-21 |
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