JP2687616B2 - Manufacturing method of printed wiring board - Google Patents

Manufacturing method of printed wiring board

Info

Publication number
JP2687616B2
JP2687616B2 JP1227716A JP22771689A JP2687616B2 JP 2687616 B2 JP2687616 B2 JP 2687616B2 JP 1227716 A JP1227716 A JP 1227716A JP 22771689 A JP22771689 A JP 22771689A JP 2687616 B2 JP2687616 B2 JP 2687616B2
Authority
JP
Japan
Prior art keywords
solder resist
photo solder
insulating substrate
manufacturing
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1227716A
Other languages
Japanese (ja)
Other versions
JPH0391293A (en
Inventor
一智 比嘉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1227716A priority Critical patent/JP2687616B2/en
Publication of JPH0391293A publication Critical patent/JPH0391293A/en
Application granted granted Critical
Publication of JP2687616B2 publication Critical patent/JP2687616B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Application Of Or Painting With Fluid Materials (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、電子機器等に使用されるプリント配線板の
製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board used in electronic equipment and the like.

従来の技術 従来、高密度のプリント配線板のソルダレジストの形
成方法は一般的に、フォト法による形成方法で行われて
いる。すなわち、第2図に示すように、絶縁基板1上に
導体回路2を形成し、その上に、フォトレジスト3を塗
布し、溶剤の一部を除去し乾燥被膜を形成する(第2図
a)。次に、マスクフィルム6を密着させ紫外光4を照
射して露光した後(第2図b)、所定の現像液で未露光
部分を溶解除去する(第2図c)。そして、残部の露光
部のフォトレジスト膜の溶剤除去及び重合硬化のため熱
硬化を行う。
2. Description of the Related Art Conventionally, a method of forming a solder resist for a high-density printed wiring board is generally performed by a photo method. That is, as shown in FIG. 2, a conductor circuit 2 is formed on an insulating substrate 1, a photoresist 3 is applied thereon, and a part of the solvent is removed to form a dry film (FIG. 2a). ). Next, after the mask film 6 is brought into close contact with the film and exposed to ultraviolet light 4 (FIG. 2B), the unexposed portion is dissolved and removed with a predetermined developing solution (FIG. 2C). Then, the photoresist film in the remaining exposed portion is thermally cured for solvent removal and polymerization curing.

発明が解決しようとする課題 このようなプリント配線板の製造方法においては、露
光の際、マスクフィルムと絶縁基板との位置合わせが通
常片側0.05〜0.1mmと極めて高い精度を要する工程であ
り、また、光の回り込み及び解像性向上のため、フィル
ムと基板とを密着させるのに、一般には真空吸着を用い
ており、露光前のセッティングに30〜60秒、真空密着に
10〜20秒、露光に20〜40秒の時間を要し、生産性を著し
く悪くするものである。
DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In such a printed wiring board manufacturing method, during exposure, alignment between the mask film and the insulating substrate is usually a step requiring 0.05 to 0.1 mm on one side and extremely high precision, and In order to wrap light around and improve the resolution, vacuum suction is generally used to bring the film and substrate into close contact with each other.
It takes 10 to 20 seconds and 20 to 40 seconds for exposure, which significantly deteriorates productivity.

本発明は、これらの課題を解決するため、露光の際、
マスクフィルムを必要とせず、マスクフィルムと絶縁基
板の位置合わせ、及び真空吸着を省略することによっ
て、生産性、精度を飛躍的に向上させることを目的とし
たものである。
The present invention, in order to solve these problems, during exposure,
The purpose of the present invention is to drastically improve productivity and accuracy by eliminating the need for a mask film, omitting the alignment between the mask film and the insulating substrate, and omitting vacuum suction.

課題を解決するための手段 この課題を解決するために本発明は、導体回路を形成
した絶縁基板上の一部又は全面にフォトソルダレジスト
を塗布し、フォトソルダレジストの硬化に適する波長を
有する光線を絶縁基板端面より入射し、絶縁基板中より
絶縁基板表面へ伝わった光線で、表面のフォトソルダレ
ジストを硬化させ、導体回路上の未露光のフォトソルダ
レジストを現像にて溶解・除去して、フォトソルダレジ
スト膜を形成する方法とするものである。
Means for Solving the Problem In order to solve the problem, the present invention is to apply a photo solder resist to a part or the whole surface of an insulating substrate on which a conductor circuit is formed, and to apply a light beam having a wavelength suitable for curing the photo solder resist. Is incident from the end surface of the insulating substrate, the light transmitted from the insulating substrate to the surface of the insulating substrate cures the photosolder resist on the surface, dissolves and removes the unexposed photosolder resist on the conductor circuit by developing, The method is to form a photo solder resist film.

作用 この製造方法によれば、フォトソルダレジスト塗布面
の導体回路がマスクフィルムの遮光部の役目をなし、導
体回路のない部分のフォトソルダレジストを硬化させマ
スクフィルムを用いず、しかも真空吸着、位置合わせ、
もすることなく、高速で、高精度なソルダレジストを形
成することができる。
Function According to this manufacturing method, the conductor circuit on the surface coated with the photo solder resist functions as a light-shielding portion of the mask film, and the photo solder resist in the portion without the conductor circuit is cured without using the mask film, and the vacuum adsorption and the position are performed. Together,
It is possible to form a solder resist with high speed and high accuracy without performing

実施例 以下、本発明の一実施例を第1図a〜dの図面を用い
て説明する。
Embodiment Hereinafter, one embodiment of the present invention will be described with reference to the drawings of FIGS.

365nmの波長の紫外線透過率が40%〜50%で、かつ一
定の厚みを保ったガラス−エポキシ基材(以下、基材と
いう)11上に導体回路12を形成する。その基材11の回路
形成面側に適正露光量500〜600mJ/cm2(塗膜厚:20〜30
μm)で、しかも、365nmの感光波長ピークを有するフ
ォトソルダレジスト13を塗布し、仮乾燥等の所定の処理
を行う(第1図a)。その後、4方向の基板端面から、
365nmの波長を有する紫外線14を入射し、基材11中を透
過させ、表面のフォトソルダレジスト13を光重合により
硬化させてフォトソルダレジスト13を形成する(第1図
b)。この際、入射する露光量は基材11の紫外線透過率
に応じて、フォトソルダレジスト13の適正露光量に達す
るように設定する。
A conductor circuit (12) is formed on a glass-epoxy base material (hereinafter referred to as "base material") (11) having a UV transmittance of 365% to 40% to 50% and maintaining a constant thickness. An appropriate exposure amount of 500 to 600 mJ / cm 2 (coating thickness: 20 to 30
μm) and a photosolder resist 13 having a peak of a wavelength of 365 nm is applied, and a predetermined process such as temporary drying is performed (FIG. 1a). After that, from the substrate end face in four directions,
Ultraviolet rays 14 having a wavelength of 365 nm are incident, transmitted through the substrate 11, and the photosolder resist 13 on the surface is cured by photopolymerization to form the photosolder resist 13 (FIG. 1b). At this time, the incident exposure amount is set so as to reach the appropriate exposure amount of the photo solder resist 13 according to the ultraviolet transmittance of the base material 11.

次に、硬化後の基板を所定の現像液(変性1−1−1
トリクロロエタン)を有する現像槽にて、1.5〜2.5kg/c
m2のスプレー圧力で30〜60秒の条件で現像する。このと
き導体回路12上のフォトソルダレジスト13は導体回路2
に遮光されて未硬化となるため、現像にて溶解・除去さ
れ、第1図cに示したようなソルダレジストの被膜を形
成する。そして、露出した導体12′を被覆するため、ス
クリーン印刷法を用いて、第1図dに示したような熱硬
化型ソルダレジスト15を形成し、フォトソルダレジスト
13′とともに熱硬化を行う。
Next, the cured substrate is treated with a predetermined developing solution (modified 1-1-1).
1.5 to 2.5 kg / c in a developing tank containing trichloroethane)
Develop under a spray pressure of m 2 for 30 to 60 seconds. At this time, the photo solder resist 13 on the conductor circuit 12 is
Since it is uncured by being shielded from light, it is dissolved and removed by development to form a solder resist film as shown in FIG. 1c. Then, in order to cover the exposed conductor 12 ', a thermosetting solder resist 15 as shown in FIG. 1d is formed by using a screen printing method, and a photo solder resist is formed.
Heat cure with 13 '.

熱硬化型ソルダレジスト15の形状においては、本発明
のフォトソルダレジスト13によって、高密度部分の形成
が終了しているため、スクリーンと基板の合致精度は、
片側0.15〜0.25mm程度となり、一般のソルダレジストの
印刷条件で容易に形成することができる。
In the shape of the thermosetting solder resist 15, since the high-density portion is formed by the photo solder resist 13 of the present invention, the matching accuracy between the screen and the substrate is
One side is about 0.15 to 0.25 mm, and it can be easily formed under the printing conditions of general solder resist.

なお、本発明に使用するフォトソルダレジストは、従
来のものよりも露光感度を高くしたものを用いることが
望ましく、また、基材の紫外線透過率を高くすることに
よって一層生産性の向上を図ることができる。さらに、
熱硬化型ソルダレジスト15は、スクリーン印刷法の紫外
線硬化型ソルダレジストに置き換えることもできる。
It is desirable that the photo solder resist used in the present invention has higher exposure sensitivity than the conventional one, and that the productivity is further improved by increasing the ultraviolet transmittance of the base material. You can further,
The thermosetting solder resist 15 can be replaced with an ultraviolet curing solder resist of screen printing method.

発明の効果 以上のように、本発明によれば、従来のフォト法によ
るプリント配線板のソルダレジストの形成で、マスクフ
ィルムや基板との位置合わせを必要とせず、また接触露
光型における真空吸着も必要としないことから、生産性
は2倍以上向上させることができる。さらに、導体が露
光の際の遮光部を形成していることから、導体回路とソ
ルダレジストの合わせズレは皆無となり、極めて精度の
高いソルダレジストを容易に形成することができる。
As described above, according to the present invention, the formation of the solder resist of the printed wiring board by the conventional photo method does not require the alignment with the mask film or the substrate, and the vacuum adsorption in the contact exposure type is also possible. Since it is not necessary, productivity can be improved more than twice. Further, since the conductor forms the light-shielding portion at the time of exposure, there is no misalignment between the conductor circuit and the solder resist, and it is possible to easily form the solder resist with extremely high accuracy.

【図面の簡単な説明】[Brief description of the drawings]

第1図a〜dは本発明の一実施例における製造方法を示
す断面図、第2図a〜cは従来のフォトソルダレジスト
の製造方法を示す断面図である。 11……ガラス−エポキシ基材、12……導体回路、13……
フォトソルダレジスト、14……紫外光、15……熱硬化型
ソルダレジスト。
1A to 1D are sectional views showing a manufacturing method in an embodiment of the present invention, and FIGS. 2A to 2C are sectional views showing a conventional method of manufacturing a photo solder resist. 11 …… Glass-epoxy base material, 12 …… Conductor circuit, 13 ……
Photo solder resist, 14 ... UV light, 15 ... Thermosetting solder resist.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】導体回路を形成した絶縁基板上に前記回路
を含む一部又は全面にフォトソルダレジストを塗布し、
フォトソルダレジストの硬化に適する波長を有する光線
を絶縁基板端面より入射し、絶縁基板中より絶縁基板表
面へ伝わった光線で、表面のフォトソルダレジストを硬
化させ、導体回路上の未露光のフォトソルダレジストを
現像にて溶解・除去してフォトソルダレジスト膜を形成
するプリント配線板の製造方法。
1. A photo solder resist is applied to a part or the whole surface including the circuit on an insulating substrate on which a conductor circuit is formed,
A light beam having a wavelength suitable for curing the photo solder resist is incident from the end surface of the insulating substrate, and the light transmitted from the insulating substrate to the surface of the insulating substrate cures the photo solder resist on the surface and unexposed photo solder on the conductor circuit. A method for manufacturing a printed wiring board, wherein a resist is dissolved and removed by development to form a photo solder resist film.
JP1227716A 1989-09-01 1989-09-01 Manufacturing method of printed wiring board Expired - Fee Related JP2687616B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1227716A JP2687616B2 (en) 1989-09-01 1989-09-01 Manufacturing method of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1227716A JP2687616B2 (en) 1989-09-01 1989-09-01 Manufacturing method of printed wiring board

Publications (2)

Publication Number Publication Date
JPH0391293A JPH0391293A (en) 1991-04-16
JP2687616B2 true JP2687616B2 (en) 1997-12-08

Family

ID=16865234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1227716A Expired - Fee Related JP2687616B2 (en) 1989-09-01 1989-09-01 Manufacturing method of printed wiring board

Country Status (1)

Country Link
JP (1) JP2687616B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105246265B (en) * 2015-11-06 2018-05-01 高德(江苏)电子科技有限公司 The production method that Rigid Flex light-sensitive surface protects soft board

Also Published As

Publication number Publication date
JPH0391293A (en) 1991-04-16

Similar Documents

Publication Publication Date Title
JP2587548B2 (en) Manufacturing method of printed wiring board
JP2687616B2 (en) Manufacturing method of printed wiring board
JP3031042B2 (en) Printed wiring board for surface mounting
JP2802079B2 (en) Manufacturing method of printed wiring board
JPH03256393A (en) Manufacture of printed wiring board
JP2994295B2 (en) Build-up printed wiring board and method of manufacturing the same
JPS59141230A (en) Formation of pattern
JP2676833B2 (en) Method for forming photoresist pattern
JPS62252989A (en) Manufacture of printed circuit board
JPH0290698A (en) Printed wiring board
JPH04186894A (en) Manufacture of printed wiring board
JPS6386550A (en) Formation of multilayer interconnection layer
JPH02186692A (en) Manufacture of printed wiring board
JPH11204414A (en) Pattern formation method
JPH02144989A (en) Method of treating printed circuit board
JPH0562894A (en) Forming method for fine pattern
KR100250265B1 (en) Method of manufacturing micropattern
JPH05198929A (en) Manufacture of printed wiring board
JPH05129764A (en) Manufacture of printed wiring board
JPS58191490A (en) Method of forming resist pattern
JPH04267582A (en) Manufacture of printed wiring board
JPS63200594A (en) Printed wiring board and manufacture of the same
JPH04180615A (en) Manufacture of semiconductor device
JPH0494588A (en) Manufacture of printed circuit board
JPH04307549A (en) Exposure filter for photosensitive material and method of exposing using it

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070822

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080822

Year of fee payment: 11

LAPS Cancellation because of no payment of annual fees