JPH026250B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a counting method using random access memory, and is intended to make effective use of memory area.

Prior Art and Problems In an automobile control system, an 8-bit microcomputer is used to capture the status of each part and perform corresponding control. At this time, there are things that need to be detected and controlled by applying a delay or filter.
Random access memory (RAM) is used as a counter for this purpose.

Figure 1 shows the main parts of an automobile controller, where 10 is a central processing unit (CPU) and 12 is a memory.
Consists of ROM (read-only memory) and RAM.
ROM is mainly used to store programs, etc., and RAM is used to store data from time to time, but in automotive control, ROM capacity is sufficient and RAM capacity is running low. 14 is an input interface circuit, 16 is an analog/digital conversion circuit, and 18 is an output interface circuit.
Digital input Id from sensors etc. placed in various parts of the automobile is passed through the input interface circuit 14, and analog input Ia is converted to digital by the A/D converter 16 and then taken into the CPU 10, and the CPU receives these input information. Based on this, a control output Oc is generated and outputted to each part of the vehicle through the output interface circuit 18. The delay necessary for control (the filter function is also delayed, for example, because it is taken in after the chattering is finished) is caused by the memory 12.
More specifically, it can be obtained by using a certain storage area of the RAM section as a counter. For example, in the case of an 8-bit microcomputer, the storage capacity of one memory address is 8 bits, but this part is used as a counter, and the operation of reading the data in the storage area, incrementing it (+1), and returning it. By repeating this at clock timing until a predetermined number is reached, the necessary delay time can be obtained. Assuming that the clock period is 5 mS, the maximum value of the 8-bit number is 255, so 255 x 5 = 1275 mS is the longest time that can be measured with an 8-bit storage area, that is, an 8-bit counter.

Such memory usage counters must be provided for the number of control items that require delays and filters; in the 1-address, 1-counter method, as the number of control items increases, many addresses in RAM are occupied, and the RAM capacity is reduced. There is a problem that there is a shortage and this causes problems in storing other data.

A counter that uses a storage area of 8 bits per address can measure 1275 mS with an LSB update cycle of 5 mS as described above, but it is rare for automobiles to require such a long delay time.
In many cases, the required delay time is several 10 mS to several 100 mS. If there are multiple events that require a delay time of 75 mS or less, the number of addresses used can be halved by dividing the 8-bit memory area of one address into the upper 4 bits and lower 4 bits and using each as an independent counter. .

Purpose of the Invention The present invention has been made focusing on the above points.
Divide the storage area and use it as a counter
This is an attempt to reduce the RAM area and make effective use of RAM.

Structure of the Invention The present invention reads data from an n-bit storage area accessed by one address signal of the memory, increments or decrements the data, and writes the data.
In a memory usage counting method that performs counting by repeating such processing, an n-bit storage area accessed by one predetermined address signal is divided into a first block consisting of lower m bits and a second block consisting of upper n-m bits. divided into blocks, and at each first predetermined timing, the n specified by the predetermined one address signal is
Read the n-bit data in the bit storage area,
By incrementing or decrementing 2° and returning to the original value, the first block in the n-bit storage area is given the function of the first counter, and at every second predetermined timing, the address signal specified by the predetermined one address signal is Read n-bit data from n-bit storage area,
The second block in the n-bit storage area functions as a second counter by incrementing or decrementing 2 ^m and returning it to the original value.Next, this will be explained with reference to an embodiment. .

Embodiment of the Invention FIG. 2 shows the RAM section of the memory 12.
RAM 12a has eight memory cells in each storage area accessed by address signal ADD. 20 is one of these 8-bit storage areas and is used as the counter described above. In the present invention, such a storage area is divided into two, into upper 4 bits and lower 4 bits, as shown in Figure b, or into upper 5 bits and lower 3 bits, as shown in Figure c. (The reverse is also possible) Divide into two and use each as an independent counter. CTR ₁ and CTR ₂ indicate these counters. In case b, each counter has 4 bits, so the maximum count value is 15, and as mentioned above, assuming the LSB update timing is every 5 mS, the maximum measurement time is 75.
mS. In case c, one counter CTR ₁ has 5 bits, so the maximum count value is 31 and the maximum measurement time is 155 mS, and the other counter CTR ₂ has 3 bits, so the maximum count value is 7 and the maximum measurement time is 35 mS.
It is S. The clock period is not 5mS, but the second
If you double, triple, etc., the time measurement will become rough, but
The maximum measurement time will be twice, three times, etc. as above. These counters CTR ₁ and CTR ₂ have the same address, so when one is read, the other is also read, and the same goes for writing. For the lower bit counter CTR ₂ in Figure 2b, the counter is incremented by the LSB in its lower bit.
(A binary 8-bit number is any one from 00 to FF when expressed in hexadecimal, but 01) is expressed as the LSB of the upper bit for the same high-order bit counter CTR ₁ , and expressed in hexadecimal as above 10 This is done by adding . The counter in FIG. 2c also conforms to this. The upper and lower bit counters CTR ₁ and CTR ₂ are read at the same time, and both counters are incremented and returned (written to the same address) as if they were running, but if no overflow occurs, they will interfere with each other. It works independently. Measures must be taken when overflow occurs.

FIG. 4 is a flowchart showing an example of how to update the counter. This processing routine is activated by an interrupt every 5 mS for a certain period of time in this example, and first increments the lower 4 bits of the counter, ie, CTR ₂ in FIG. 2b. Next, it is checked whether an overflow has occurred, and if it has not occurred (N), the upper 4 bits of the counter, that is, CTR ₁ in FIG. and wait for the next interrupt. When an overflow occurs (Y) by incrementing the upper/lower 4 bits, the upper/lower 4 bits are decremented (-1) to cancel the overflow.

In this state, the upper/lower 4 bits will stick to the maximum value (oscillate between 15 and 16).

Figure 5 shows the lower 4-bit counter CTR ₂ for 50mS.
As a counter, or as an upper 4-bit counter
The processing procedure when using CTR ₁ as a 20mS counter is shown below. When sensors placed in various parts of a car are composed of switches (contacts), such as idle sensors, the contacts have chattering, so even if a detection signal rises, it is not immediately captured, and it is not possible to obtain a stable signal after the chattering ends. It is better to take it in after the condition is reached. Here, the input that requires a delay of 50 mS is designated as A, and the input that requires a delay of 20 mS is designated as B.
When this processing routine starts, first, input A is read and it is checked whether A="0".

As shown in Figure 3a, when the sensor is not producing a detection output, A="0", and in this state (Y), the lower 4-bit counter CTR ₂ is repeatedly incremented and cleared, and the count value is 0. It's getting old. It is checked whether this count value has reached 50 mS (has it reached 10 assuming the LSB update cycle is 5 mS), and if no (N), input B is read and B = “0”.
If so (Y) clear the upper 4 bit counter CTR ₁ , then check whether it has reached 20mS,
If no (N), return to the first reading of input A, and repeat the same operation. When inputs A and B become "1", counting is started as shown in FIG. 3b and e. Then, when it reaches 50 mS and 20 mS, in this example, when the count value reaches 10 and 4, it is set as a timeout and inputs A and B are taken as true values.

The counters CTR ₁ and CTR ₂ continue counting even after counting 50 mS and 20 mS, and eventually reach the maximum value and are held at the maximum value as described in FIG. Reset occurs when inputs A and B return to zero.

The counters CTR ₁ and CTR ₂ can be used not only to increase the count value by incrementing, but also to a counting method in which a certain value is initially preset and then decremented to gradually decrease the count value. Counter CTR ₂ on input A and counter on input B
The process of assigning CTR ₁ (processing such as looking at the upper 4 bits and looking at the lower 4 bits) is done in the program, and 01 is assigned to CTR ₂ .
The program also performs the same process of incrementing CTR ₁ by adding 10 (both in hexadecimal). Furthermore, in the embodiment, when the counter reaches the maximum value, it repeats incrementing and decrementing to maintain the maximum value, but the counter may stop counting at the maximum value. Furthermore, in the embodiment, it is a clock (timer) because it counts clock cycles of a constant period, but if the signal to be counted has an irregular period, it is of course a mere counter, and the present invention can of course be applied to the latter.

Effects of the Invention As explained above, according to the present invention, it is possible to effectively utilize the RAM storage area used as a counter.
It is extremely effective and suitable for applications where RAM capacity tends to be insufficient.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the main parts of the vehicle controller, Fig. 2 is an explanatory diagram of the RAM section used as a counter, Fig. 3 is an explanatory diagram of the counting operation, and Figs. 4 and 5 show the timekeeping procedure. It is a flowchart. In the drawing, 12a is a memory, 20 is an n-bit storage area, and CTR ₁ and CTR ₂ are blocks divided into a plurality of blocks.

Claims (1)

[Claims] 1 n accessed by 1 memory address signal
In a memory usage counting method in which data in a bit storage area is read, incremented or decremented and written, and this process is repeated for counting, the n-bit storage area accessed by one predetermined address signal is divided into lower m bits (m <n) and a second block consisting of upper n-m bits, and at each first predetermined timing, the n bit storage area designated by the predetermined one address signal is By reading the n-bit data, incrementing or decrementing it by 2 degrees, and returning it to the original value, the first block in the n-bit storage area has the function of the first counter, and the predetermined 1 is read at every second predetermined timing. By reading the n-bit data in the n-bit storage area specified by the address signal, incrementing or decrementing 2 ^m and returning to the original value, the second block in the n-bit storage area has the function of a second counter. Characteristic memory usage counting method.