JPS5738030A - Counter circuit - Google Patents

Counter circuit

Info

Publication number
JPS5738030A
JPS5738030A JP11313880A JP11313880A JPS5738030A JP S5738030 A JPS5738030 A JP S5738030A JP 11313880 A JP11313880 A JP 11313880A JP 11313880 A JP11313880 A JP 11313880A JP S5738030 A JPS5738030 A JP S5738030A
Authority
JP
Japan
Prior art keywords
ram3
data
input pulse
counter
sets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11313880A
Other languages
Japanese (ja)
Inventor
Takahiro Minami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11313880A priority Critical patent/JPS5738030A/en
Publication of JPS5738030A publication Critical patent/JPS5738030A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To give count function, by using a part of area of data memory in one- chip microcomputer for a counter and adding 1 to this memory area when an input pulse is present. CONSTITUTION:When an input pulse PIN is detected at a count controlling circuit CONT1, the end of a microcomputer instruction is judged and the next instruction is interrupted with the discrimination of the end. The circuit CONT1 outputs a row address and sets the data to read out the inversion R/W from an RAM3, and the readout data of the RAM3 is applied to a program counter PC4. An incrementor INC5 adds 1 to the content of a counter PC4 and the circuit CONT1 sets the signal inversion R/W to write-in side, and the added data is written in the same location of the RAM3 and counts the input pulse PIN once.
JP11313880A 1980-08-18 1980-08-18 Counter circuit Pending JPS5738030A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11313880A JPS5738030A (en) 1980-08-18 1980-08-18 Counter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11313880A JPS5738030A (en) 1980-08-18 1980-08-18 Counter circuit

Publications (1)

Publication Number Publication Date
JPS5738030A true JPS5738030A (en) 1982-03-02

Family

ID=14604516

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11313880A Pending JPS5738030A (en) 1980-08-18 1980-08-18 Counter circuit

Country Status (1)

Country Link
JP (1) JPS5738030A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160218A (en) * 1984-01-30 1985-08-21 Matsushita Electric Ind Co Ltd Programmable frequency divider
JPS60211590A (en) * 1984-04-06 1985-10-23 Fujitsu Ten Ltd Counting method utilizing memory

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160218A (en) * 1984-01-30 1985-08-21 Matsushita Electric Ind Co Ltd Programmable frequency divider
JPH0467374B2 (en) * 1984-01-30 1992-10-28 Matsushita Electric Ind Co Ltd
JPS60211590A (en) * 1984-04-06 1985-10-23 Fujitsu Ten Ltd Counting method utilizing memory
JPH026250B2 (en) * 1984-04-06 1990-02-08 Fujitsu Ten Ltd

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