JPS56153436A - Storage device of received data for coupling of electronic computer - Google Patents
Storage device of received data for coupling of electronic computerInfo
- Publication number
- JPS56153436A JPS56153436A JP5612580A JP5612580A JPS56153436A JP S56153436 A JPS56153436 A JP S56153436A JP 5612580 A JP5612580 A JP 5612580A JP 5612580 A JP5612580 A JP 5612580A JP S56153436 A JPS56153436 A JP S56153436A
- Authority
- JP
- Japan
- Prior art keywords
- data
- ram17
- received data
- circuit
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
PURPOSE:To read out data with the relative addresses from a processor without hampering the bus use right of the processor and enhance the processing efficiency of the processor by storing received data into a memory without using any common bus. CONSTITUTION:The rise of the strobe signal SB from a terminal device is detected with a strobe signal rise detecting circuit 12. From a control circuit 13, the latch request signal LT is supplied to a received data register 11. In the register 11, the channel number CH and input data DT are latched. The channel number output CN from the register 11 is applied to the 1st address conversion circuit 14 and circuit 13, and the received data OD are applied to an RAM17. A circulating counter 15 is controlled by the circuit 13 to output the change-over signal to set a selector 16 to the write side from the counter 15 and the write address of the RAM17 is determined by the selector 16, so that the data OD are written in the prescribed area of the RAM17. The data are read out from the RAM17 at the address determined by the 2nd address conversion circuit 18.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5612580A JPS56153436A (en) | 1980-04-30 | 1980-04-30 | Storage device of received data for coupling of electronic computer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5612580A JPS56153436A (en) | 1980-04-30 | 1980-04-30 | Storage device of received data for coupling of electronic computer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56153436A true JPS56153436A (en) | 1981-11-27 |
Family
ID=13018344
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5612580A Pending JPS56153436A (en) | 1980-04-30 | 1980-04-30 | Storage device of received data for coupling of electronic computer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56153436A (en) |
-
1980
- 1980-04-30 JP JP5612580A patent/JPS56153436A/en active Pending
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