SU1580376A1 - Device for addressing memory units - Google Patents

Abstract

The invention relates to automation and computing and can be applied to address memory blocks of different sizes. The purpose of the invention is to expand the field of application of the device by organizing a continuous field of addresses for memory blocks of various sizes. The device contains input 1 for setting the base address, group of adders 2, group of comparison blocks 3, group of blocks 4 for memory of different volume, input 5 for specifying the current address, input 6 for setting the memory size. Output 7 serves to further expand the device or may be the input of setting the base address for another device. 1 il.

Description

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The invention relates to automation and computing and can be used to address memory blocks of various sizes.

The purpose of the invention is to expand the use of the device due to the organization of a continuous address field for memory blocks of various sizes.

The drawing shows a block diagram of a device for addressing memory blocks.

The device contains input 1 for setting the base address of the device, group of adders 2, group of blocks 3 for comparison, group of blocks 4 for memory, input 5 for the current address of the device and input 6 for specifying the amount of memory. Output 7 is the output of the device for further expansion if two or more devices are used.

The device works as follows.

In advance, input 1 is supplied in some way with the code of the base address, from which the assignment of addresses to the memory blocks begins, and the information about the volumes of the memory blocks in blocks 2 is written from the corresponding inputs 6 of the block memory capacities.

Let the base number be 000, and the memory capacity of the first block 4 be A, the volume of the second memory block 4 be A2, and so on, of the n-th block An. Then the output of the first adder is the sum

,

A0 + A

where A0 000,

at the output of the second adder amount

 -A + D + D - A 2 A01L2 1g

and so on, and at the output of the last adder the sum

 - S -f dp - PM ny

At the end of the summation process, the following codes are found on the first and third inputs of comparison units 3: on the first block 3,000 and A, on the second block 3 and, on block n

and i,.

Therefore, the i-adder adds the start address with the total capacity of the 1st block to get the start address of the next block.

When accessing the memory bays, the current is fed to the input 5 of the device

the address, and the comparison blocks 3 determine whether the current address is in the ranges specified by (totalizer) or not,

If the input address Ah satisfies the requirement

A „, U

OX1 1 /

then the first memory block is energized. If the input address satisfies the requirement

-,BUT ,

then the second memory block is energized. If the input address satisfies the requirement

"-,BUT ",

then the last memory block is energized.

The output 7 of the last adder 2 contains the code for the total capacity of the memory system.

The use of inputs 6 for specifying the memory capacity will allow using the device in memory systems where there is a set of blocks with different (non-DI-RAD) memory sizes, for example, using a device for assembling a system of partially usable crystals of limited volumes or memory chips having different capacity which expands the field of application of this device.

Claims (1)

In addition, the device can collect unallocated amounts of memory in computing systems at a given point in time for their more efficient use. Invention Formula A device for addressing memory blocks containing a group of adders, a group of comparison blocks, a group of memory blocks, the output of the 1st comparison block being connected to the sample input of the 1st memory block (, 2, ..., p), operand inputs all comparison blocks are connected to the input of the current address of the device, the upper boundary input of the 1st comparison block is connected to the output of the 1st adder, the first input of the 1st adder is the input of the set memory size of the 1st memory block of the device, output 1- the adder is connected to the second input (i + l) -ro of the adder, the output of the n-th adder is is an output for further expansion of the device; va, and the second input of the first adder of the continuous address field is the input of setting the base memory for memory of different sizes, of the res device, which distinguishes the e-input of the lower boundary of the 1st block, is equal to the fact that, in order to expand the hub, it is connected to the second input of the 1st block application areas of the device due to the adder.