JPS5914765B2 - Digital control device input circuit - Google Patents

Description

[Detailed description of the invention] The invention cycles digital input signals.

The present invention relates to an input circuit for reliably reading digital input signals regardless of the length of the pulse width of the digital input signals in a digital control device that performs reading control. Conventionally, an example of an input circuit for this type of digital control device is shown in FIG.

In the figure, 10 is an arithmetic processing unit (hereinafter referred to as CPU);
1 is a CPU bus, 2... is an input control unit, 21 is a group selection signal, 21-1 is a first group selection signal forming the group selection signal 21, and 21-n is a first group selection signal forming the group selection signal 21. 100 is the digital input signal of the first group, 101 to 171 are the 8-bit digital input signals constituting the digital input signal 100 of the first group, and 102 to 1T2 are the digital inputs. Signals 101-171
Signal conversion circuits 103 to 173 are signal conversion circuits 102 to 172 for converting the signal into a signal format that is easy to process.
The digital signal outputs 104 to 1T4 are the digital signals 103 to 1T4 depending on the selection signal 21-1 of the first group.
173 to the input data bus 22;
5 to 1T5 are input data selected by selection circuits 104 to 1T4. Next, the operation shown in FIG. 1 will be explained. The input control unit 20 sends and receives input data to the CPU 10.
The CPU bus 11 connects the CPUIO and the input control section 20. The CPU bus 11 receives the group number of required input data, that is, the address signal and C
It consists of a control signal that controls the timing with PUIO and input data. The input control unit uses the address signal and control signal from the CPUIO to generate a group selection signal 20 for selecting input data requested by the CPUIO.
is sent to the selection circuit. This group selection signal 21 consists of n selection signals from the first group selection signal 21-1 to the nth group selection signal 21-n, and only one group among them is selected at one instant. It's getting old. The digital input signals simultaneously selected by this selection signal are 8 bits. That is, the digital input signals 101 to 171 are selected by the selection signal 21-1 of the first group.
A first group of digital input signals 100 consisting of the following is selected by the selection circuits 104 to 174 and outputs input data to the input data bus 22. This input data bus 22 has a bus configuration in which signals of the same bit order of 8-bit digital input signals of each group are connected by logical sum, and the input data selected by the group selection signal 21 is sent to the CPUIO via the input control unit 20. Sent and read. Therefore, CPUlO
By sending an address signal and a control signal from the address signal to the input control section 20, the digital input signal of the group corresponding to the address signal can be read as input data.
By sequentially changing this address signal, that is, the group number of input data, digital input signals of all groups can be read. In order to monitor the status of the digital input signal, the CPUIO does not always read such digital input signals, and generally the CPUIO does not continue to read the digital input signal in order to monitor the status of the digital input signal. The reading cycle is determined, and this operation can be repeated cyclically. Since the input circuit of a conventional digital control device is configured to read digital input signals cyclically as described above, it is possible to reliably detect the presence or absence of a narrow pulse-like digital input signal, such as a trip signal of a protection relay. In order to detect all the information without fail, the reading cycle must be shortened. On the other hand, if the reading cycle is shortened, the CPU occupancy rate increases and other functions stop working.

That is, the pulse width of the digital input signal cannot be made below a certain value, and there is a limit. Moreover, to solve this drawback, an external auxiliary memory circuit is required as an interface, which is expensive. This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and each digital input circuit stores bit signals constituting input data, and upon completion of sending input data to an arithmetic processing section. If the bit signal of the input data is in a significant state, the stored contents are maintained, and on the other hand, if the bit signal of the input data is not in the significant state when the sending of the input data is completed, the stored contents are reset. It is an object of the present invention to provide an economical input circuit for a digital control device that can reliably read digital input signals without omission regardless of the pulse width of the digital input signals. An embodiment of the present invention is shown in FIGS. 2 and 3 below.

In the figure, the same reference numerals as in FIG. 1 are used for the same components as in the prior art. In FIG. 2, 106 to 176 are storage circuits 107 to 176 for storing whether or not the digital input signals 101 to 171 are in a significant state or not.
177 is the output of the memory circuits 106 to 176; 30 is the output of the memory circuit 106 at the time of starting up and resetting the digital control device;
This is a master clear signal for resetting 176. Digital input signals 101 to 171 are sent to signal conversion circuit 1
02-172 perform signal conversion, and the outputs 103-173 are applied to input terminals of memory circuits 106-176. Memory circuits 106-176 receive digital input signals 101-17.
1 becomes a significant state, and its output 107~17
7 is added to the selection circuits 104 to 174 as input data,
It is sent to the input data bus 22 by the first group selection signal 21-1 and read into the CPUIO. The memory circuits 106 to 176 complete the selection of the first group, that is, the CPU
When the reading of IO is completed, it is determined whether or not to reset the memory contents. Memory circuit 106~
176 does not reset the stored contents when the digital input signals 101 to 171 are in a significant state upon completion of reading, but resets the stored contents when they are not in a significant state. That is, when the reading of the input data is completed, the storage circuits 106 to 176 set the stored contents to the state of the digital input signals 101 to 171 at that time, regardless of the stored contents so far, and then set the stored contents to the state of the digital input signals 101 to 171 at that time, and It is designed to memorize the presence or absence of a digital input signal to be obtained. That is, when the reading of the input data is completed (the reset function sets the memory circuits 106 to 175 to the state of the digital input signals 101 to 171, and stores the presence or absence of the next digital input signal. The second group selection signal 21-2 to the nth group selection signal 21 constitute the group selection signal 21 in this manner.
-n can be sequentially switched to read the digital input signals of each group into the CPUIO. FIG. 3 shows a specific circuit example of the memory circuit 106 as an example to specifically explain the operation of the memory circuits 106 to 176 shown in FIG. In FIG. 3, 106-1 is the input data terminal D
, a D-type flip-flop having a trigger terminal T1, an output terminal Q, and a set-reset terminal S, D, 106-
2 is an "L" level signal applied to the input data terminal D.

The trigger terminal T of this D type flip-flop is the first
It operates to store the information on the input data terminal D and send it to the output terminal Q only when the group selection signal 21-1 changes from "H" to "L" level. However, this operation is designed to operate only when there is no signal at the set terminal S1 or the set terminal R. The signals on the set terminal S1 and the reset terminal R can preferentially set/reset this flip-flop. 4a-c1 and 5a-c are time charts of the D flip-flop 106-1, which is a storage circuit. Among these, FIGS. H” → “L”
This is for the case where the digital input signal 103 is not in a significant state at the time of change, and FIGS. 5a to 5c are for the case when the digital input signal 103 is in a significant state at the completion of reading. In addition to the S terminal of the type flip-flop, the digital signal 103 also indicates that the digital signal 103 has become a significant state, that is, that it has become "L" → "H" → "L", or that it has become a significant state. That is, it memorizes that it is at the "H" level and sets the output terminal Q to the "H" level. On the other hand, the selection signal 21-1 of the first group changes from "L" to "H" to [L
” level, and when reading of the first group of input data is completed during the “H” level period, the signal changes from “H” to “L” level depending on the state of the digital signal 103 applied to the S terminal. The output terminal Q is as follows. When the digital signal 103 is already at the "L" level, the trigger terminal T operates effectively and the input data terminal D "
The "L" level signal is stored and the output terminal Q is set to the "L" level. On the other hand, when the digital signal 103 is at the "H" level, the operation of the trigger terminal T is disabled and the output terminal Q remains at the "H" level. Note that 30 is a master signal for setting the D type flip-flop 106 in a reset state. In this way, memory circuits 106 to 176 in FIG. 2 can be constructed using D type flips. In the above embodiment, one of the digital input signals
Although the explanation has been made assuming that each group is 8 bits, the same effect as in the above embodiment can be obtained even if the number of bits constituting one group is changed. Although a D-type flip-flop is used as a specific example of the memory circuit, the gist of the present invention is to memorize the presence or absence of an input signal and, after completion of reading into the CPU, determine whether or not to set it based on the state of the input signal. The present invention relates to an input circuit for resetting a memory circuit, and the circuit configuration of the memory circuit and peripheral circuits are not limited to the above example. As described above, according to the present invention, an input circuit of a digital control device that reads input signals cyclically and performs arithmetic processing includes a storage circuit that stores the presence or absence of an input signal, and after completion of reading the input signal, a memory circuit that stores the presence or absence of the input signal. By resetting the memory circuit or providing a set circuit, it is possible to construct a highly reliable and economical input circuit that can reliably read input signals with short pulse widths without increasing the CPU occupation rate. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an input circuit of a conventional digital control device, FIG. 2 is a block diagram showing an example of the input circuit of the present invention, and FIG. 3 is a specific example of the memory circuit shown in FIG. Circuit diagrams, Figures 4a-c are time charts of the memory circuit when the pulse width of the digital input signal is narrow, and Figures 5a-c are time charts of the memory circuit when the pulse width of the digital input signal is wide. . 10...CPU, 11...CPU bus, 20...Input control unit, 21...Group selection signal, 21-1... First group selection signal, 22... Input data bus, 100...
...First group digital input signal, 103~
173...Digital signal, 104-174.
...Selection circuit, 105-175...Input data, 105-176...Storage circuit, 107
~177... Output of memory circuit, 30...
・Master clear signal.

Claims (1)

[Claims] 1. An arithmetic processing section that performs arithmetic processing on input data; an input control section that sequentially controls a plurality of digital input circuits according to commands from the arithmetic processing section; In a digital control device comprising a plurality of digital input circuits that send input data to the arithmetic processing section, each of the digital input circuits may include:
In addition to storing the bit signals constituting the input data, if the bit signals of the input data are in a significant state when the sending of the input data to the arithmetic processing unit is completed, the stored contents are maintained; 1. An input circuit for a digital control device, comprising a plurality of memory circuits that reset the memory contents when a bit signal of input data is not in a significant state upon completion of transmission.