KR900007548Y1 - Apparatus for compensating clock pulse rate in hdlc - Google Patents

Abstract

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Description

Self-Clocked Air Compensation and Recovery Circuit

1 is a circuit diagram according to the present invention.

2 is a detailed circuit diagram of the clock rate correction circuit 50 of FIG. 1 according to the present invention.

3 is an operating waveform diagram according to the present invention.

4 is a flow chart for realizing the present invention.

* Explanation of symbols for main parts of the drawings

10: central processing unit 20: transmission and reception buffer memory

30: HDLC controller 40: parallel input / output circuit

50: clock rate correction circuit 11-14: latch

21-23: Bus Transceiver 31-36: Counter

41, 42: Multiplexer

The present invention relates to clock error correction in the use of a High Level Date Link Control (HDLC) controller capable of performing a link protocol of a link layer. In particular, the transmit / receive clock rate (Rate) is the HDLC controller. The present invention relates to a self clock rate error correction and recovery circuit that is capable of recovering to a normal state by automatically correcting a clock rate when data transmission is interrupted because it is faster than a mast clock rate of.

In general, the order of the high-level data link layer (hereinafter referred to as "HDLC") is to divide an arbitrary bit length information into a transmission unit called a frame, and to include a command included in the control information in the frame. It is a transmission control sequence, that is, a protocol, which enables information to be continuously transmitted without being restricted by a code by using response information.

The frame structure has 8 bits of flag, address, and control, n bits of information, and 16 bits of frame check sequence. The link control sequence is divided into two order classes of commands and responses, and defines how to use them.

Specific technical details of the HDLC are described in detail in pages 558 to 605 of Appendix "Ohm," "Data Communication and Computer Network."

When the HDLC protocol is conventionally used, a dedicated chip of an HDLC controller is mainly used. The dedicated chip of the HDLC controller is WD2511 of "West Digital" of a US semiconductor company, and its function is capable of data format and error checking. Synchronization timing and blocks are designated by software, and are provided to transmit and receive information frames in HDLC order. However, if the transmit / receive clock rate is too fast compared to the master clock of the HDLC controller, an error occurs in the clock rate, resulting in a bit error in frame data transmission / reception.

At this time, there was a problem in that data transmission was stopped and data transmission and reception were impossible.

Accordingly, an object of the present invention is to provide a circuit capable of automatically reducing data transmission and reception to a normal state by correcting a clock error according to a speed difference between a transmit / receive clock rate and a master clock rate of an HDLC.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram according to the present invention, 10 is a central processing unit, 20 is a memory for transmitting and receiving buffer, 30 is HDLC controller, 40 is a parallel input / output circuit (PIO), 50 is a clock rate correction circuit, 11-14 is a latch, 21-23 are bus transceivers, 31-36 are counters, and 41-42 are multiplexers.

The parallel input / output circuit 40 can be made by Z80-P10 of the US "Zylog Corporation", the counters 31-36 can be made by 74LS1611, and the multiplexers 41 and 42 can be made by 74LS352.

Bus transceivers 21, 22, and 23 are connected to the data bus DO-D7 of the central processing unit 10, and latches 11 and 13 from the address bus AO-A15 of the central processing unit 10. Data bus (DO-D7) is connected, the output terminal (BO-B7) of the bus transceiver 21 is connected to the data bus (DO-D7) of the HDLC controller 30, the HDLC controller (30) Is connected to the data bus DO-D7 of the latch 12, and the address buses A8-A15 are connected to the data bus DO-D7 of the latch 14. Each output terminal QO-Q7 of 11-14 is connected to the address bus AO-A15 of the transmission / reception buffer memory 20, and the output terminal AO-A7 of the bus transceiver 22 is the transmission / reception buffer. The data bus DO-D7 of the memory 20 is connected to each other, and the bus transceiver 23 and the data bus DO-D7 of the parallel input / output circuit 40 are interconnected to each other. Request to send (RTS) Transmitted data (TD: Transmitted Data) is connected to the transmit request terminal (RTS) and the transmit terminal (TD) of the HDLC controller 30, and the transmit permission terminal (CTS: Cleat to send) and the receiver (CTS) of the second line receiver 62 ( RD: Received Data) is connected to the transmit permission stage CTS and the receive stage RD of the HDLC controller 30, and the clocks of the first and second clock stages CK1 and CK2 are counters 31, 33, 34, 36. The output of the ripple output terminal RCO of the counters 33 and 36 is inputted to the clock terminal CLK of the counters 32 and 35. The outputs of the counters 31 and 34 or the first or the first output terminals Q4 and QB are connected to the selection terminals G and S of the multiplexers 41 and 42 so as to output the output terminals QA and QB. Transmit and receive clock stages of the HDLC controller 30 by selecting clocks of the clock stages CK1 and CK2 through the line receiver 62. The signal of the correction enable line 52 generated from the output terminal PA1 of the parallel input / output circuit 40 and the interrupt signal terminal of the HDLC controller 30. Is input to the clock rate correction circuit 50, and the output terminal PA1 of the parallel input / output circuit 40 is connected to the enable terminals EN and P of the counters 31-36 through the inverter 204. The output terminal Q of the clock rate correction circuit 50 is connected to a clear terminal of the counters 32 and 35. And a data set preparation stage of the second line receiver 63 connected to the input terminal PB1 of the parallel input / output circuit 40. : Connect the Data Set Ready Data to the input terminal (PBO) of the parallel input / output circuit 40, and connect the Data Terminal Ready terminal (DTR: Data Terminal Ready) of the line driver 61 to the input terminal (PAO) of the parallel input / output circuit 40. Connect.

FIG. 2 is a detailed circuit diagram of the clock rate correction circuit 50 of FIG. 1 according to the present invention. The output terminal PA1 of the parallel input / output circuit 40 is connected to the clock terminal CK of the flip-flop 202. , Interrupt stage of the HDLC controller 201 Is connected to the input terminal A of the multivibrator 201, and the multivibrator 201 is 74LS121. The output terminal Q of the multivibrator 201 is connected to the data terminal D of the flip-flop 202. The output terminal Q of the deflip-flop 202 is cleared from the counters 32 and 35. And an input terminal PB1 of the parallel input / output circuit 40.

3 is an operation waveform diagram according to the present invention, where (3a) waveform is the basic clock of the HDLC controller 30, and (3b) waveform is the interrupt stage of the HDLC controller 30 of FIG. Waveform (3C) is the output signal of the output terminal Q of FIG. 2 multivibrator 201, and (3d) waveform is the output of output terminal PA1 of the parallel input / output circuit 40 of FIG. The output of the correction enable line 52 of the clock rate correction circuit 50, and the waveform (3e) is the output signal of the output terminal Q of the deflip-flop 202, and the waveform (3F) is the multiplexer 42. (3g) is the output of the ripple carry output (RCO) of the counters (33, 36), (3h) is the output (out) of the corrected multiplexer (42). Is the receive clock (RC) signal.

4 is a flow chart of the HDLC controller 30 for realizing the present invention, and the flow chart of FIG. 4 can be processed while accommodating the same functions as the microcomputer in the HDLC controller 30. When the HDLC controller 30 transmits / receives data according to CCITT recommendation x, 25 levels, the data of the transmit / receive buffer memory 20 is used.

First, the control of the central processing unit 10 transmits the data of the transmission / reception buffer memory 20 to the HDLC controller 30 or transfers the processed data to the transmission / reception buffer memory 20. Is executed accordingly.

When the CPU 10 stores the data processed by the HDLC controller 30 in the transmission / reception buffer memory 20. A write control signal is generated to enable the write and receive buffer memory 20. And a predetermined signal is applied to an input terminal IAO-IA3 capable of reading the value of the internal I / O register of the HDLC controller 30 through the address bus AO-A7, and the HDLC controller 30 is output by the output of the read I / O register. Enable latches 12 and 14 to output an address signal, input the address of the data to be stored and stored in the address bus AO-A15 of the transmission / reception buffer memory 20, and set the HDLC controller in the designated area. Received data output from 30 are stored in the transmission / reception buffer memory 20 through the bus transceivers 21 and 22.

When the pre-stored data of the transmitted buffer memory 20 is transmitted, the read control stage of the central processing unit 10 is transmitted. By generating a control signal, the read control signal of the transmission / reception buffer memory 20 Is entered. The latches 11 and 13 are enabled by the address latch enable end ALE to input an address output through the address bus AO-A17 into the transmission / reception buffer memory 20 to designate a address to be read. .

The data of the designated address of the transmit / receive buffer memory 20 is input to the HDLC controller 30 through the bus transceiver 21 and at the same time the data bus (DO−) of the parallel input / output circuit 40 through the bus transceiver 23. D7).

At this time, the HDLC controller 30 receives a signal generated through the address bus AO-A7 of the central processing unit 10 to the input terminal IAO-IA3 of the HDLC controller 30 and is generated from an input / output register. By this, it is possible to input the read data of the transmission / reception buffer memory 20. The counters 31, 33, 34, and 36 count clocks of the clock stages CK1 and CK2 respectively input through the first line receiver 62.

When a predetermined count is counted by the counters 33 and 36, a ripple is generated and input to the clock stage CLK of the counters 32 and 35, and counted again by the counters 32 and 35.

According to the counting result of the counters 32 and 35, the outputs of the output terminals QA and QB of the counters 32 and 35 are input to the selection terminals G and S of the multiplexers 41 and 42 and thus the selection stage ( Transmit and receive clock stages TC and RC of the HDLC controller 30 by selecting the input clocks of the clock stages CK1 and CK2 of the counters 31 and 34 and the first line receiver 62 according to the input logic of G and S. It is configured to supply as a clock signal, but the steady state date / time counters 31 to 36 are disabled to supply the input clocks of the clock terminals CK1 and CK2 of the first line receiver 62 directly.

However, if the clock error occurs during normal operation of the HDLC controller 30, the interrupt terminal When the control signal is generated and input to the clock rate correction circuit 50, the counting of the counters 32 and 35 is controlled by the output of the clock rate correction circuit 50, and the output terminal of the parallel I / O circuit 40 ( The state of PA1 enables the counters 31-36 via the inverter 204.

The output divided by the counters 31 and 34 is selected and supplied by the multiplexer 42 in accordance with the outputs of the output terminals QA and QB of the counters 32 and 35. The selected clock is supplied to the correction clock according to the clock error of the HDLC controller 30. When the clocks of the transmit / receive clock stages RC and TC are returned to their normal state, the clock rate correction circuit 50 returns to the initial state and disables the counters 31 to 36 so that the multiplexer is output by the counters 32 and 35. At 41 and 42, the clocks of the clock terminals CK1 and CK2 of the first line receiver 62 are received.

Therefore, if a specific embodiment of the present invention will be described in detail with reference to FIGS. 1 to 4, the HDLC controller 30 processes the register status predetermined register periodically by an interrupt routine as shown in FIG. Read on.

Three status registers are set in the HDLC controller 30. The status register stores a value of a clock error state generated during operation so that the clock error state can be read.

Therefore, the value of the status register is read in step (4a) and the HDLC controller 30 checks whether the packet receiver is set from the value of the status register in step (4b). In step 4c, it is checked whether a receiver ready bit is set when the packet receiver is set in step 4b. When the receiver ready bit is set in step (4c), it is cleared in step (4e) and when the receiver ready bit is not set, it is checked in step (4d) whether the transmission clock bit for block transmission is set.

When the transmission block bit is set, the loopback test is checked at (4g) and the loopback test is performed at the loopback test, and the loopback test (4g) is not the transmission block bit set at (4d). If not, it is checked in (4f).

When it is not an error in step 4f, the HDLC controller 30 inputs data to the bus transceiver 21 and inputs the data to the parallel input / output circuit 40 through the bus transceiver 23.

The parallel input / output circuit 40 receives the data and sets the output terminal PA1 of the parallel input / output circuit 40 to "high". At this time, " high " of the output terminal PA1 of the parallel input / output circuit 40 is input to the clock terminal CK of the deflip-flop 202 of the clock rate correction circuit 50.

On the other hand, since the "high" of the output terminal PA1 of the parallel I / O circuit 40 becomes "low" through the inverter 204 to disable the counters 31-36, the outputs of the counters 32 and 35 are multiplexed. Only the clocks of the clock stages CK1 and CK2 of the first line receiver 62 are selected at 41 and 42 to be supplied to the normal clocks of the transmission and reception clock stages TC and RC of the HDLC controller 30.

However, when the error state is in step (4f), the value of the error register storing the error value is read in step (4h).

When the error register value is "AIH", check whether the address is loaded through the latches 12 and 14 in the process (4j). If the address is being loaded, it waits and if it is not the address load, it switches to the read mode in the process (4I) After monitoring, the address signal is transmitted to the latches 12 and 14.

However, if it is not " AIH " in step (4i), check whether 01H or 02H is applied in step (4n, 4o). When 01H or 02H in the process (4n, 4o), the data is output to the bus transceiver 21 in the process (4K) and input to the parallel input / output circuit 40 through the bus transceiver 23. At this time, the output terminal PA1 of the parallel input / output circuit 40 is set to "low (0)". The counter 31-36 is output by inputting the " low " state of the output terminal PA1 of the parallel input / output circuit 40 to the clock rate correction circuit 50 and inverting the inverter 204 by outputting the " high ". Enable it.

If 5, 6 and 7 bits of the status register for interrupt processing are set in the real HDLC controller 30, the interrupt terminal Is in the "low" state as shown in (3b). If an error occurs during the data processing of the HDLC controller 30 when the fifth bit of the status register is set, an error value is input to an error register for processing as an error. Save it. Step (4h) is a process of reading the error register value.

Interrupt stage as in (3b) above When it is "low", the state of the output terminal Q of the multivibrator 201 is generated as shown in (3c).

In this case, since the output terminal PA1 of the parallel input / output circuit 40, that is, the node 52 of FIG. 2 is " low " The output of the deflip-flop 202 changes at the positive edge of (3d) input to CK), so that the " high " state remains as shown in (3e).

However, when the state of the node 52 of the clock rate correction circuit 50, that is, the signal (3d) is inverted in the inverter 204, counting is started by enabling the counters 31-36.

When the counters 33 and 36 generate a predetermined counting to the ripple carry stage RCO as in (3g) and are input to the clock stage CLK of the counters 32 and 35, the output stage QA of the counters 32 and 35 , The outputs of the counters 31 and 34, which are inputted to the selection terminals G and S of the multiplexers 42 and 41 of the QB and counted the clock input as in (3F), are selected and the correction time as in (3h). It is inputted to and corrected by the transmit / receive clock terminals RC and TC of the HDLC controller 30.

Once the clock is corrected and returned to the normal state, the HDLC controller 30 moves the output stage PA1 of the parallel input / output circuit 40 to the high clock stage CK of the deflip-flop 202 as shown in (3d). Is entered.

As described above, the output terminal Q of the deflip-flop 202 at the positive edge is " low " as shown by (3e) to clear the counters 32 and 35. At the same time, it is " low " through inverter 204 to disable counters 31-36. Then, the clocks of the clock stages CK1 and CK2 of the first line receiver 62 are normally supplied to the HDLC controller 30 through the multiplexers 42 and 41.

As described above, since the correction according to the clock rate error is automatically executed, the data transmission and reception clock can be used as the data transmission and reception clock.

Claims (1)

The latches 11-13 are connected to the central processing unit 10 from the address bus AO-A15 of the HDLC controller 30, and a bus transceiver is connected to the data bus DO-D7 of the HDLC controller 30. 21), the bus transceivers 22 and 23 are connected from the bus transceiver 21 and the data bus DO-D7 of the central processing unit 10, and are transmitted and received buffers from the latches 11-14. The address bus (AO-A15) of the memory 20 for connection, the data bus (DO-D7) of the memory 20 for the transmission and reception buffer from the bus transceiver 22, and the HDLC controller 30 Interrupt) And the clock correction enable line 52 of the parallel input / output circuit 40 to the clock rate correction circuit 50, and the output terminal Q of the clock rate correction circuit 50 clears the counters 32 and 35. Connect the terminal CLR, connect the inverter 204 from the line 52, connect the output terminal of the inverter 204 to the enable terminals P, EN of the counters 31-36, The ripple carry output terminal RCO of the counters 33 and 36 is connected to the clock terminal CLK of the counters 32 and 35, and the multiplexer 41 of the output terminals QA and QB of the counters 32 and 35. And select terminals (G, S) of 42 and the output terminals of the multiplexers (41, 42) are connected to the transmit / receive clock terminals (TC, RC) of the HDLC controller 30. Self clock rate error correction and recovery circuit.