JPH05122253A - Line controller - Google Patents

Abstract

PURPOSE:To provide the line controller with high reliability especially in the case of high speed transmission by implementing smoothly hand-shake between the line controller and a processor. CONSTITUTION:The line controller provided with a read/write means storing communication data sent/received synchronously with a transfer speed of the communication data sent through a communication line tentatively in a buffer 3 and implementing read/write of the data stored in the buffer 3 and with a counter 2 counting data quantity stored in the buffer 3 is featured to be devised in such a way that a count of the counter 2 is stored to any of plural registers 15 storing the count of the counter 2 upon the receipt of frame end data included in the communication data and the count stored in the register 15 is sent when a read signal sent from the read/write means is applied to the line controller.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line control device which is a data communication device and uses a FIFO buffer for data transmission and reception.

[0002]

2. Description of the Related Art In synchronism with the transfer rate of communication data transmitted via a communication line, the communication data to be transmitted and received is temporarily stored in a buffer, and the communication is performed at a speed different from the data storage speed in the buffer. In a line controller equipped with a read / write means for reading and writing data, the handshake between the line controller and the processor generally takes a form in which the processor side reacts to the action from the line controller. .. For example, JP-A-62-22
Japanese Patent No. 5050 discloses a line control device having the configuration shown in FIG. That is, in FIG. 5, a serial / parallel converter 4 for converting a serial signal supplied from a telecommunication line into a parallel signal for every n bits is a first-in first-out (hereinafter FIFO) storing the n-bit parallel data as one word.
Connected to the memory 3. The write request strobe pulse signal sent from the serial / parallel converter 4 is sent to the AND circuit 6 connected to the up-count terminal of the up-down counter 2. The output side of the AND circuit 6 is also connected to the FIFO memory 3.

On the other hand, the other input terminal of the AND circuit 6 is
Data obtained by inverting the output data of the up / down counter 2 by the inverter 8 is supplied. When the output value of the up / down counter 2 is 7 or less, the output data of the up / down counter 2 passes through the AND circuit 6, and the count value of the up / down counter 2 is counted up.
It is also sent to the IFO memory 3. Therefore, the FIFO memory 3 stores the word data sent by the serial / parallel converter 4. In this way, the FIFO memory 3 stores a plurality of word data.

The processor 1 is connected to the input unit 7 via the bus 5, and the output side of the up / down counter 2 is connected to the input unit 7. Therefore, the processor 1 can read the count value of the up / down counter 2 by accessing the input unit 7. The count value is 1 to 7
If so, the processor 1 determines that there is word data to be read in the FIFO memory 3, and the up / down counter 2
The read request strobe pulse signal is sent to the AND circuit 9 connected to the down count terminal of the. AND circuit 9
3 input N to which the output data of the up / down counter 2 is inverted and supplied by the inverter 10 to the other input terminal of
The output side of the AND circuit 11 is connected, and the AND circuit 9 allows the output data of the up / down counter 2 to pass when the output data is 1 or more. The output side of the AND circuit 9 is also connected to the FIFO memory 3,
When data is sent from the ND circuit 9, the count value of the up / down counter 2 counts down, and
The read strobe pulse signal is supplied to the O memory 3, and the processor 1 can read the word data from the FIFO memory 3. As described above, in the conventional circuit control device, the processor 1 can recognize the number of used stages of the FIFO memory 3 by the up / down counter 2.

[0005]

Now, consider the case where data of consecutive frames as shown in FIG. 6 is received. In this case, an interrupt is called from the line control side after receiving the flag, but when the processor 1 is in a state where it is not possible to immediately make a reaction, for example, the processor 1 is also in charge of the control inside the system and its priority is given. If the rank is higher, as shown in FIG. 7, a situation may occur in which the count value of the up / down counter 2 is read after the first n bytes of the second frame have already been received.

In such a case, the processor 1 can read from the first frame although the data amount of the data relating to the first frame which remains without being read from the FIFO memory 3 is actually a byte, for example. There is a problem in that the byte amount is erroneously recognized as a + n bytes, and the data is processed as invalid data reception after decoding the data of the first and second frames.

Further, as a method of using the conventional line control device as shown in FIG. 5, (i) a huge counter and a register for counting the number of bytes of one frame are provided separately from the circuit of FIG. When 1 receives a frame end, a method of determining the end of the data of the first frame by an internal operation after reading the register, (ii) a protocol in which the number of data bytes in the frame is given as information, for example, A method of using HDLC or the like to hold the value during the reception of one frame and determining the end of the data of the first frame by an internal calculation is considered.

The above method (i) operates as shown in FIG. The main operation will be explained. In step (indicated by S in the figure), the software counter is set to 0 and the FIFO
Each time the data stored in the memory 3 is read, at step 5, the count value of the software counter is incremented by 1 and the count value of the software counter is incremented. When the data stored in the FIFO memory 3 is exhausted and the frame end signal in the received data is received, the count value of the software counter is subtracted from the count value of the frame counter in step 9 to obtain the count value Cnt ', and the count value concerned. When Cnt 'becomes 0, reception of one frame is completed.

Further, the method (ii) performs the operation as shown in FIG. 9, and as described in steps 6 and 7, holds the data byte numerical value during one frame reception using the protocol, In step 9, the software counter value is subtracted from the data byte value to obtain the count value Cnt ', and when the count value Cnt' becomes 0, the reception of one frame is completed.

However, the above method (i) requires hardware +
Although it is a solution by software, there are problems that the amount of hardware increases and that internal calculation requires time, and the processor 1 is burdened accordingly. While above
Method (ii) is a software solution,
It depends on the protocol, and a new factor of erroneous recognition of the number of data bytes due to transmission error is added. Further, as described above, there is a problem due to the internal calculation. The present invention has been made to solve the above problems,
It is an object of the present invention to provide a highly reliable line control device that smoothly performs a handshake between the line control device and a processor and particularly when performing high-speed transmission.

[0011]

According to the present invention, communication data transmitted and received in synchronization with the transfer rate of communication data transmitted through a communication line is temporarily stored in a buffer, and at a speed different from the storage speed in the buffer. In a line control device having a read / write means for reading and writing the stored data from the buffer and a counter for counting the amount of data stored in the buffer, the count value of the counter is held. When multiple frame registers and frame end data included in the communication data are supplied,
When a register selection means for selecting the register for storing the count value of the counter and a read signal sent by the read / write means are supplied, the register selected by the register selection means is stored in the register. And a count value sending means for sending the count value stored therein, and in addition to the above-mentioned constituent features, the present invention provides
The read / write means includes: an interrupt control unit that generates an interrupt signal when frame end data included in the communication data is supplied; and a remaining amount register that stores the remaining amount of the storage capacity of the buffer. The remaining amount stored in the remaining amount register is read, and the amount of the communication data corresponding to the remaining amount is stored in the buffer.

By adopting such a configuration, the register selected by the register selecting means is a counter for counting the amount of communication data transmitted / received in synchronization with the transfer rate of the communication data transmitted through the communication line. Stores a numerical value. The count value sending means sends the count value stored in the register from the register when the read signal sent by the read / write means is supplied. Therefore, the high-speed line control device can easily recognize the frame delimiters in continuous frame reception, and acts to enhance the reliability of high-speed transmission control.

Further, the interrupt control section reads the interrupt signal when the frame end data is supplied.
The read / write means reads out the remaining amount data of the buffer storage capacity stored in the remaining amount register.
Therefore, the provision of these components makes it possible to easily recognize the frame delimiters, and thus acts to reduce the software load such as calculation in the line control device.

[0014]

FIG. 1 shows an embodiment of the line control device of the present invention.
5, the same components as those in FIG. 5 are designated by the same reference numerals and the description thereof will be omitted. When the frame end pulse signal included in the received data, which is a signal indicating the end of the frame, is supplied, the register group that holds the value of the up / down counter 2 at the frame end and the select control circuit 15 are connected to the up / down counter 2. The output side is connected, and the output side of the register group and the select control circuit 15 is connected to the bus 5. The frame end pulse signal is also supplied to the interrupt control circuit 16, and the interrupt control circuit 16 sends out a signal indicating that the frame end pulse signal has been supplied to the processor 1. or,
The output side of the processor 1 is connected to the AND circuit 9, the interrupt control circuit 16, the register group and the select control circuit 15 via the read selector 30. The read selector 30 has, for example, a circuit configuration as shown in FIG.
A select signal and a read strobe signal for selecting which of the FIFO memory 3 or the register group and the select control circuit 15 should read the data are supplied from the processor 1, and the select signal causes the FIFO memory 3 or the register group and the select control circuit 15 to read. The read strobe signal is sent to either one. The read strobe pulse signal sent from the read selector 30 to the register group and the select control circuit 15 is also sent to the interrupt control circuit 16.

The register group and select control circuit 15 are
For example, as shown in FIG. 2, flip-flops 17 and 1
It is composed of 8- and 4-bit registers 19 and 20, and buffer groups 26 and 27. In this embodiment, the count bit width of the up / down counter 2 is 4 bits, that is, FI.
Maximum allowable data amount of FO memory 3 is 16 bytes, FIF
This shows a case where the maximum allowable number of consecutive frames, which indicates how many frames of data can be stored in the O memory 3, is 3. The count value output terminal of the up / down counter 2 is connected in parallel to the data input terminals of the registers 19 and 20, respectively, and the operation of the data output terminal of the register 19 is controlled by the control signal sent from the OR circuit 25. The data output terminal of the register 20 is connected in parallel to a buffer group 26 composed of buffers for bits, and similarly, the data output terminal of the register 20 has a buffer group 27 for 4 bits whose operation is controlled by a control signal sent from the OR circuit 24. Are connected in parallel. The output side of each of the buffer groups 26 and 27 is connected to the bus 5.

The output data terminal of the flip-flop 17 to which the frame end pulse signal is supplied as a clock pulse signal through the inverter 21 has an AND circuit 2 whose output side is connected to the clock input terminal of the register 19.
Connected to 2. The frame end pulse signal is supplied to the other input terminal of the AND circuit 22. The inverted output data terminal of the flip-flop 17 is connected to the AND circuit 23 whose output side is connected to the clock input terminal of the register 20 together with the input terminal of the flip-flop 17. Therefore, the count value of the up / down counter 2 is stored in one of the registers 19 or 20 by the output signals of the AND circuits 22 and 23 whose frame end pulse signal is supplied and whose signal level is changed by the output signal of the flip-flop 17. To be done.

On the other hand, the output data terminal of the flip-flop 18 to which the inverted signal of the read strobe pulse signal (hereinafter referred to as the inverted read strobe pulse signal) sent from the processor 1 is supplied to the clock pulse signal input terminal is O.
It is connected to the R circuit 24. The inverted read strobe pulse signal is supplied to the other input terminal of the OR circuit 24,
As described above, the output side of the OR circuit 24 is connected to the control terminal of each buffer forming the buffer group 27.
The inverted output data terminal of the flip-flop 18 is connected to the OR circuit 25 together with the input terminal of the flip-flop 18. An inverted signal of the read strobe pulse signal is supplied to the other input terminal of the OR circuit 25, and the output side of the OR circuit 25 is connected to the control terminal of each buffer forming the buffer group 26 as described above. .. Therefore,
The output data of the flip-flop 18 is changed by the inverted read strobe pulse signal sent from the processor 1,
When the output signals of the OR circuits 24 and 25 change accordingly, the bus 5 of the stored value of either the register 19 or 20
Is controlled.

The operation of the high-speed line control device of the present invention constructed as above will be described below with reference to FIG. The operation of storing / reading the communication data into / from the FIFO memory 3 and the counting operation of the up / down counter 2 during the storage / reading operation are the same as those described above, and therefore the description thereof will be omitted. When the communication data is supplied to the device and the frame end pulse signal in the communication data is supplied to the flip-flop 17 in step 2, a signal is sent from either the AND circuit 22 or 23 by the output signal of the flip-flop 17. Then, the count value of the up / down counter 2 is stored in either the register 19 or 20 corresponding to the AND circuits 22 and 23. It is to be noted that which of the registers stores the count value is determined by the flip-flop 1
7 depends on whether it is in the set state or the reset state in the initial state, and depends on the circuit design of the device. The frame end pulse signal is also supplied to the interrupt control circuit 16,
The signal supplied by the processor 1 allows the processor 1 to recognize how many times the frame end pulse signal has been supplied.

In step 5, register 19 or 2
When the processor 1 reads the count value stored in 0, when the processor 1 receives the first frame end interrupt signal from the interrupt control circuit 16,
The read strobe pulse signal is sent to the register group and the flip-flop 18 in the select control circuit 15 via the read selector 30. Therefore, at this time, only the buffer 27 is opened and the data stored in the register 20 is sent to the bus 5. The level of the output signal of the flip-flop 18 is inverted at the rising edge of the read strobe pulse signal, that is, at the same time when the read operation is completed. Next, when the frame end pulse signal is issued, only the buffer 26 is opened by the read strobe pulse signal of the processor 1, and the data stored in the register 19 is sent to the bus 5.
In this way, the processor 1 can read out the register by simply sending the read strobe pulse signal.
Since 0, register 19 and register 20 change in this order,
The processor 1 does not need to be aware of which register should be accessed.

As the flip-flop 18, one having the same initial state as that of the flip-flop 17 is selected. For example, if the flip-flop 17 is in the reset state, the flip-flop 18 is also selected in the reset state. Therefore, the count value is read from the register which stores the count value of the up / down counter 2 when the frame end pulse signal is finally supplied to the device, and is supplied to the processor 1 via the bus 5.

As described above, in the present high-speed line control device, the current count value of the up / down counter 2 at the frame end, that is, the number of remaining bytes of the FIFO memory 3 is
Since the registers are held in the register group and the register in the select control device 15, the processor 1 can easily recognize the frame delimiters in continuous frame reception, and the reliability of high-speed transmission control can be improved. Further, since the processor 1 can easily recognize the frame delimiter by reading the value stored in the remaining frame byte register at the end of the frame, the software load such as internal calculation performed in step 5 shown in FIG. 8 and FIG. And a smooth handshake between the buffer and the FIFO memory can be performed.

In the above embodiment, the register group and the select control circuit 15 are provided with two 4-bit registers. However, the number of bits of the registers is not limited to this, and the FIFO memory of the FIFO memory can be changed. It is possible to cope with a change in data capacity, and it is possible to increase the maximum allowable number of consecutive frames by increasing the number of registers.

[0023]

As described above in detail, according to the present invention, when the frame end data is supplied, the count value of the communication data amount is held in the register, so that the frame delimiter can be easily received in the continuous frame reception. Can be recognized, the reliability of high-speed transmission control can be improved, and the frame delimiter can be easily recognized, so that the software load such as calculation in the line control device can be reduced, and the buffer and read / A handshake with the writing means can be performed smoothly.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a high-speed line control device of the present invention.

FIG. 2 is a circuit diagram showing an example of a configuration of a register group and a select control circuit shown in FIG.

FIG. 3 is a logic circuit diagram showing a configuration of a read selector shown in FIG.

4 is a flowchart showing an operation of the high-speed line control device shown in FIG.

FIG. 5 is a block diagram showing a configuration of a conventional line control device.

FIG. 6 is a diagram showing reception data in which frames are consecutively supplied to the line control device.

FIG. 7 shows the used capacity of the FIFO memory and the processor 1 and the FIF when the data of consecutive frames is received.
It is a figure for demonstrating the access state with O memory.

FIG. 8 is a flowchart showing an operation of a conventional line control device.

FIG. 9 is a flowchart showing an operation of a conventional line control device.

[Explanation of symbols]

1 ... Processor, 2 ... Up-down counter, 3 ... FI
FO memory, 15 ... Register group and select control circuit,
16 ... Interrupt control circuit.

Claims (3)

[Claims] 1. A buffer for temporarily storing communication data to be transmitted and received in synchronization with a transfer rate of communication data transmitted through a communication line, and to store the stored data from the buffer at a speed different from the storage speed in the buffer. In a line control device comprising a read / write means for performing a read / write operation and a counter for counting the amount of data accumulated in the buffer, a plurality of registers for holding the count value of the counter, the communication When the frame end data contained in the data is supplied, the register selecting means for selecting the register for storing the count value of the counter, and the register when the read signal sent by the read / write means is supplied. Count value transmitting means for transmitting the count value stored in the register from the register selected by the selecting means, A line control device characterized in that 2. The read / write operation comprises: an interrupt control unit that generates an interrupt signal when frame end data included in the communication data is supplied; and a remaining amount register that stores the remaining amount of storage capacity of the buffer. The line control device according to claim 1, wherein the writing means reads the remaining amount stored in the remaining amount register and stores the communication data in an amount corresponding to the remaining amount in the buffer. 3. A read / write operation for temporarily storing data to be transmitted / received in synchronism with the speed of a communication line in a buffer, and reading and writing the stored data from the buffer at a speed different from the speed at which the buffer is stored. In a line controller provided with a writing means and a counter for counting the amount of data accumulated in the buffer, a plurality of registers for holding the count value of the counter and frame end data included in the data are supplied. The register selection means for selecting the register for storing the count value of the counter, and the register selected by the register selection means when the read signal sent by the read / write means is supplied. The count value sending means for sending the stored count value and the frame end data included in the communication data are supplied. An interrupt control unit that generates an interrupt signal when the input signal and a remaining amount register that stores the remaining amount of the storage capacity of the buffer are provided, and the read / write means reads the remaining amount stored in the remaining amount register, A line control device, characterized in that an amount of the communication data corresponding to the remaining amount is stored in the buffer.