JPH0251255B2 - - Google Patents

Info

Publication number
JPH0251255B2
JPH0251255B2 JP58051711A JP5171183A JPH0251255B2 JP H0251255 B2 JPH0251255 B2 JP H0251255B2 JP 58051711 A JP58051711 A JP 58051711A JP 5171183 A JP5171183 A JP 5171183A JP H0251255 B2 JPH0251255 B2 JP H0251255B2
Authority
JP
Japan
Prior art keywords
layer
region
emitter
polycrystalline silicon
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58051711A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58201358A (ja
Inventor
Maikeru Kemureeji Baanaado
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS58201358A publication Critical patent/JPS58201358A/ja
Publication of JPH0251255B2 publication Critical patent/JPH0251255B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H10D10/441—Vertical BJTs having an emitter-base junction ending at a main surface of the body and a base-collector junction ending at a lateral surface of the body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/1414—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/92—Controlling diffusion profile by oxidation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/965—Shaped junction formation

Landscapes

  • Bipolar Transistors (AREA)
JP58051711A 1982-05-18 1983-03-29 浅いエミツタ構造を持つトランジスタを製造する方法 Granted JPS58201358A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/379,535 US4437897A (en) 1982-05-18 1982-05-18 Fabrication process for a shallow emitter/base transistor using same polycrystalline layer
US379535 1982-05-18

Publications (2)

Publication Number Publication Date
JPS58201358A JPS58201358A (ja) 1983-11-24
JPH0251255B2 true JPH0251255B2 (enExample) 1990-11-06

Family

ID=23497662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58051711A Granted JPS58201358A (ja) 1982-05-18 1983-03-29 浅いエミツタ構造を持つトランジスタを製造する方法

Country Status (4)

Country Link
US (1) US4437897A (enExample)
EP (1) EP0094482B1 (enExample)
JP (1) JPS58201358A (enExample)
DE (1) DE3380889D1 (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4534806A (en) * 1979-12-03 1985-08-13 International Business Machines Corporation Method for manufacturing vertical PNP transistor with shallow emitter
US4573256A (en) * 1983-08-26 1986-03-04 International Business Machines Corporation Method for making a high performance transistor integrated circuit
US4523370A (en) * 1983-12-05 1985-06-18 Ncr Corporation Process for fabricating a bipolar transistor with a thin base and an abrupt base-collector junction
JPS6146063A (ja) * 1984-08-10 1986-03-06 Hitachi Ltd 半導体装置の製造方法
US4663825A (en) * 1984-09-27 1987-05-12 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US4701780A (en) * 1985-03-14 1987-10-20 Harris Corporation Integrated verticle NPN and vertical oxide fuse programmable memory cell
US4635345A (en) * 1985-03-14 1987-01-13 Harris Corporation Method of making an intergrated vertical NPN and vertical oxide fuse programmable memory cell
GB8507624D0 (en) * 1985-03-23 1985-05-01 Standard Telephones Cables Ltd Semiconductor devices
JPS62208638A (ja) * 1986-03-07 1987-09-12 Toshiba Corp 半導体装置の製造方法
US4721685A (en) * 1986-04-18 1988-01-26 Sperry Corporation Single layer poly fabrication method and device with shallow emitter/base junctions and optimized channel stopper
US4812417A (en) * 1986-07-30 1989-03-14 Mitsubishi Denki Kabushiki Kaisha Method of making self aligned external and active base regions in I.C. processing
US4829015A (en) * 1987-05-21 1989-05-09 Siemens Aktiengesellschaft Method for manufacturing a fully self-adjusted bipolar transistor
US4774204A (en) * 1987-06-02 1988-09-27 Texas Instruments Incorporated Method for forming self-aligned emitters and bases and source/drains in an integrated circuit
US4784966A (en) * 1987-06-02 1988-11-15 Texas Instruments Incorporated Self-aligned NPN bipolar transistor built in a double polysilicon CMOS technology
US5005066A (en) * 1987-06-02 1991-04-02 Texas Instruments Incorporated Self-aligned NPN bipolar transistor built in a double polysilicon CMOS technology
US5270224A (en) * 1988-03-11 1993-12-14 Fujitsu Limited Method of manufacturing a semiconductor device having a region doped to a level exceeding the solubility limit
US5518937A (en) * 1988-03-11 1996-05-21 Fujitsu Limited Semiconductor device having a region doped to a level exceeding the solubility limit
KR910005403B1 (ko) * 1988-09-23 1991-07-29 삼성전자 주식회사 고성능 바이폴라 트랜지스터 및 그 제조방법
DE69033711T2 (de) * 1989-04-25 2001-06-28 Matsushita Electronics Corp., Kadoma Verfahren zur Herstellung eines bipolaren Transistors
US5117271A (en) * 1990-12-07 1992-05-26 International Business Machines Corporation Low capacitance bipolar junction transistor and fabrication process therfor
DE69714575D1 (de) * 1997-05-30 2002-09-12 St Microelectronics Srl Laterales PNP-bipolares elektronisches Bauelement und dessen Herstellungsverfahren
DE10231407B4 (de) * 2002-07-11 2007-01-11 Infineon Technologies Ag Bipolartransistor
DE10254663B4 (de) * 2002-11-22 2005-08-04 Austriamicrosystems Ag Transistor mit niederohmigem Basisanschluß und Verfahren zum Herstellen

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2449688C3 (de) 1974-10-18 1980-07-10 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung einer dotierten Zone eines Leitfähigkeitstyps in einem Halbleiterkörper
JPS51127682A (en) 1975-04-30 1976-11-06 Fujitsu Ltd Manufacturing process of semiconductor device
US4104086A (en) 1977-08-15 1978-08-01 International Business Machines Corporation Method for forming isolated regions of silicon utilizing reactive ion etching
US4160991A (en) 1977-10-25 1979-07-10 International Business Machines Corporation High performance bipolar device and method for making same
US4190466A (en) 1977-12-22 1980-02-26 International Business Machines Corporation Method for making a bipolar transistor structure utilizing self-passivating diffusion sources
US4157269A (en) 1978-06-06 1979-06-05 International Business Machines Corporation Utilizing polysilicon diffusion sources and special masking techniques
US4234362A (en) 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
JPS5586151A (en) 1978-12-23 1980-06-28 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor integrated circuit
US4234357A (en) 1979-07-16 1980-11-18 Trw Inc. Process for manufacturing emitters by diffusion from polysilicon
US4319932A (en) * 1980-03-24 1982-03-16 International Business Machines Corporation Method of making high performance bipolar transistor with polysilicon base contacts

Also Published As

Publication number Publication date
EP0094482B1 (en) 1989-11-23
US4437897A (en) 1984-03-20
JPS58201358A (ja) 1983-11-24
EP0094482A2 (en) 1983-11-23
EP0094482A3 (en) 1986-10-08
DE3380889D1 (en) 1989-12-28

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