JPH0237097B2 - - Google Patents

Info

Publication number
JPH0237097B2
JPH0237097B2 JP57208892A JP20889282A JPH0237097B2 JP H0237097 B2 JPH0237097 B2 JP H0237097B2 JP 57208892 A JP57208892 A JP 57208892A JP 20889282 A JP20889282 A JP 20889282A JP H0237097 B2 JPH0237097 B2 JP H0237097B2
Authority
JP
Japan
Prior art keywords
wiring conductor
members
bumps
conductor members
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57208892A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5999794A (ja
Inventor
Takashi Nagasaka
Toshio Sonobe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP57208892A priority Critical patent/JPS5999794A/ja
Publication of JPS5999794A publication Critical patent/JPS5999794A/ja
Publication of JPH0237097B2 publication Critical patent/JPH0237097B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
JP57208892A 1982-11-29 1982-11-29 厚膜回路装置 Granted JPS5999794A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57208892A JPS5999794A (ja) 1982-11-29 1982-11-29 厚膜回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57208892A JPS5999794A (ja) 1982-11-29 1982-11-29 厚膜回路装置

Publications (2)

Publication Number Publication Date
JPS5999794A JPS5999794A (ja) 1984-06-08
JPH0237097B2 true JPH0237097B2 (en, 2012) 1990-08-22

Family

ID=16563849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57208892A Granted JPS5999794A (ja) 1982-11-29 1982-11-29 厚膜回路装置

Country Status (1)

Country Link
JP (1) JPS5999794A (en, 2012)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59163891A (ja) * 1983-03-08 1984-09-14 富士通株式会社 セラミツク配線板
JPH0695519B2 (ja) * 1985-12-26 1994-11-24 株式会社東芝 バンプ形成方法
JP2787230B2 (ja) * 1989-07-29 1998-08-13 イビデン株式会社 電子部品塔載用基板
JP5110042B2 (ja) * 2005-01-25 2012-12-26 セイコーエプソン株式会社 デバイス実装方法
WO2016114358A1 (ja) 2015-01-16 2016-07-21 株式会社村田製作所 基板、基板の製造方法及び弾性波装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5259571A (en) * 1975-11-11 1977-05-17 Oki Electric Ind Co Ltd Substrate for face down bonding
JPS54137661A (en) * 1978-04-18 1979-10-25 Ngk Spark Plug Co Method of producing integrated circuit board

Also Published As

Publication number Publication date
JPS5999794A (ja) 1984-06-08

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