JPH0236045U - - Google Patents

Info

Publication number
JPH0236045U
JPH0236045U JP11568388U JP11568388U JPH0236045U JP H0236045 U JPH0236045 U JP H0236045U JP 11568388 U JP11568388 U JP 11568388U JP 11568388 U JP11568388 U JP 11568388U JP H0236045 U JPH0236045 U JP H0236045U
Authority
JP
Japan
Prior art keywords
integrated circuit
positioned above
circuit chip
internal structure
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11568388U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11568388U priority Critical patent/JPH0236045U/ja
Publication of JPH0236045U publication Critical patent/JPH0236045U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の実施例を示す集積回路の内部
構造図、第2図は従来の半導体集積回路の内部構
造図である。 1……プラスチツクモールド、2……リードフ
レーム、3……集積回路チツプ、4……集積回路
チツプ表面、5……リード、6……外来ノイズ、
7……実装プリント、8……リード挿入用ホール
、9……プリント配線。
FIG. 1 is a diagram of the internal structure of an integrated circuit showing an embodiment of the present invention, and FIG. 2 is a diagram of the internal structure of a conventional semiconductor integrated circuit. 1... Plastic mold, 2... Lead frame, 3... Integrated circuit chip, 4... Integrated circuit chip surface, 5... Lead, 6... External noise,
7... Mounting print, 8... Hole for lead insertion, 9... Print wiring.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] デユアルインライン型プラスチツクモールドに
封止される集積回路の内部構造において、集積回
路の実装面を最下面の基準として、上方に、集積
回路チツプ次に、該集積回路チツプをマウントし
たリードフレームを位置させることを特徴とした
集積回路。
In the internal structure of an integrated circuit sealed in a dual-in-line plastic mold, the integrated circuit chip is positioned above the mounting surface of the integrated circuit, and then the lead frame on which the integrated circuit chip is mounted is positioned above. An integrated circuit characterized by:
JP11568388U 1988-09-01 1988-09-01 Pending JPH0236045U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11568388U JPH0236045U (en) 1988-09-01 1988-09-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11568388U JPH0236045U (en) 1988-09-01 1988-09-01

Publications (1)

Publication Number Publication Date
JPH0236045U true JPH0236045U (en) 1990-03-08

Family

ID=31357564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11568388U Pending JPH0236045U (en) 1988-09-01 1988-09-01

Country Status (1)

Country Link
JP (1) JPH0236045U (en)

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