JPS6255354U - - Google Patents
Info
- Publication number
- JPS6255354U JPS6255354U JP1985146750U JP14675085U JPS6255354U JP S6255354 U JPS6255354 U JP S6255354U JP 1985146750 U JP1985146750 U JP 1985146750U JP 14675085 U JP14675085 U JP 14675085U JP S6255354 U JPS6255354 U JP S6255354U
- Authority
- JP
- Japan
- Prior art keywords
- stud
- heat dissipation
- package
- stage
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000017525 heat dissipation Effects 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 230000005855 radiation Effects 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
第１図は本考案に係るＩＣパツケージの装着状
態を示す断面図、第２図Ａ，Ｂは本考案に係る放
熱スタツドの斜視図、第３図は従来のＩＣパツケ
ージの装着状態を示す断面図、である。
図において、１はチツプ、２はステージ、３は
インナーリード、５はプリント配線基板、６はス
ルーホール、７は配線パターン、８は放熱スタツ
ド、９は放熱パターン、である。
FIG. 1 is a cross-sectional view showing how the IC package according to the present invention is installed, FIGS. 2A and B are perspective views of the heat dissipation stud according to the present invention, and FIG. 3 is a cross-sectional view showing how the conventional IC package is installed. , is. In the figure, 1 is a chip, 2 is a stage, 3 is an inner lead, 5 is a printed wiring board, 6 is a through hole, 7 is a wiring pattern, 8 is a heat radiation stud, and 9 is a heat radiation pattern.
Claims (1)
ージ用ステージ２の下部に放熱スタアド８を設け
、該スタツド８を放熱パターン９を設けたプリン
ト配線基板５のスルーホール６に挿着して使用す
ることを特徴とする半導体パツケージ。 A heat dissipation stud 8 is provided at the bottom of a stage 2 for a resin molded package on which a semiconductor chip 1 is mounted, and the stud 8 is used by being inserted into a through hole 6 of a printed wiring board 5 provided with a heat dissipation pattern 9. semiconductor package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985146750U JPH0333068Y2 (en) | 1985-09-26 | 1985-09-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985146750U JPH0333068Y2 (en) | 1985-09-26 | 1985-09-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6255354U true JPS6255354U (en) | 1987-04-06 |
| JPH0333068Y2 JPH0333068Y2 (en) | 1991-07-12 |
Family
ID=31059500
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985146750U Expired JPH0333068Y2 (en) | 1985-09-26 | 1985-09-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0333068Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014013908A (en) * | 2006-04-06 | 2014-01-23 | Freescale Semiconductor Inc | Molded semiconductor package with integrated through hole technology (tht) heat spreader pin and method of manufacturing the same |
-
1985
- 1985-09-26 JP JP1985146750U patent/JPH0333068Y2/ja not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014013908A (en) * | 2006-04-06 | 2014-01-23 | Freescale Semiconductor Inc | Molded semiconductor package with integrated through hole technology (tht) heat spreader pin and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0333068Y2 (en) | 1991-07-12 |