JPH02281360A - Asynchronous data transfer system - Google Patents

Abstract

PURPOSE:To shorten a data transfer time by defining a meaning of validation at each time of inverting the signal level of a control signal line to communicate a control signal between the master side and the slave side to communicate the control signal between the master and the slave once in each data transfer cycle. CONSTITUTION:At the time of data transfer from a master side 1 to a slave side 2, the master side 1 writes the start address of data transfer in an address signal line 4 and sets a signal AS* 3 to the low level as the validate level. By this setting, the start address is indicated to the slave side 2 and the start of data transfer is indicated. Simultaneously, a signal WR* line 5 is set to the low level as the write cycle indicating level and it is indicated to the slave side 2 that the data transfer is in the write direction. Thereafter, data is written in a data signal 8 by the master side in a first write cycle, and the first level of a DS signal line 6 is inverted to a corresponding level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a master device such as a processor, a memory and an
In a computer system consisting of slave devices such as O and an asynchronous data transfer bus connecting them, when data is transferred by executing one or more write or read data transfer cycles between the master and slave, The present invention relates to an asynchronous data transfer method for exchanging control signals between a master side and a slave side at high speed for each data transfer cycle.

[Conventional technology]

Conventionally, in computer systems, etc., when data transfer is performed by executing one or more data transfer cycles between a master side and a slave side connected by an asynchronous data transfer bus, the following procedure is generally used. Ta. First, the master side instructs the slave side to start data transfer and the direction of data transfer. After that, each data transfer cycle starts, which is writing data from the master side to the slave side (write cycle) or reading data from the slave side to the master side (read cycle). Here, the signal line that provides control signals from the master side to the slave side is connected to a data strobe (hereinafter referred to as DS).
) signal line, the signal line that gives a control signal from the slave side to the master side is called an acknowledge (hereinafter ACK) signal line, and it becomes valid in response to either the high or low level of the DS signal line or ACK signal line. or invalid is defined, and control signals are transmitted in each data transfer cycle depending on the level.

FIGS. 4 and 5 show timing charts of conventional control signal exchange between master and slave in each data transfer cycle.

Figure 4 is a timing chart of the write cycle;
The figure is a timing chart of the read cycle. In the figure, the signal lines with a "fist" mark on their names are signal lines defined so that low level is valid and high level is invalid. '' Those without a mark are signal lines for which no particular meaning is defined for the level. In Figures 4 and 5, both the DS signal line and the ACK signal line are
An example is shown in which low level is defined as valid. Further, a solid line with an arrow indicates the association of level changes of each signal, and a dotted line with an arrow indicates the propagation delay of the signal. In the notation of signal line output, when it is on the top, it is high level, when it is on the bottom, it is low level, when it is on both sides, it is either high or low level, and when it is in the middle, it is high impedance state. .

The conventional operation of each write or read data transfer cycle during data transfer will be described below with reference to FIGS. 4 and 5.

First, the master side 51 receives an ACK from the slave side 52.
After confirming that the fist signal line 57 is at an invalid level (58), data is written onto the bus (59) in a write cycle 73 (FIG. 4), and data is written on the bus (59) in a read cycle 74 (FIG. 5). In this state, both DSS double signals 53 are set to the valid level (60). By setting the DS-signal line 53 to the valid level on the master side 51, the slave side 52 is instructed to start data transfer. .

On the slave side 52, after confirming that the DS skew signal line 53 is at a valid level, data is read from the bus in a write cycle 73 (62).

In the read cycle 74, necessary data is written to the bus (63), and then the ACK umbrella signal line 57
is set to a valid level (64).

By setting the ACK signal line 57 to a valid level on the slave side 52, it instructs the master side 52 that the data transfer has been completed.

After confirming that the ACK* signal line 57 is at a valid level, the master side 51 finishes writing data in a write cycle 73 (66), and reads data from the bus in a read cycle 74. 67)
, then return the DS fist signal line 53 to the invalid level (68
), the master side 51 returns the DS/signal line 53 to an invalid level, thereby instructing the slave side 52 that the valid level of the ACK umbrella signal line 57 has been received.

On the slave side 52, after confirming that the DS signal line 53 is at an invalid level, it remains as it is in the case of a write cycle 73, and ends writing data to the bus in the case of a read cycle 74 (70). After that, both AC
By returning the Ka signal/signal 57 to the invalid level (71) and returning the ACK skew signal line 57 to the invalid level on the slave side 52.

It instructs the master side 51 that one data transfer cycle has ended and that it is possible to start the next data transfer cycle.

The above is one data transfer cycle, and the data transfer cycle is repeated as necessary. When all data transfer cycles are completed, the master side instructs the slave side to end the data transfer.

[Problem to be solved by the invention]

As explained above, in the conventional technology.

Since valid or invalid meaning is defined for the level of the signal line, DS, which is a control signal, is used between master and slave.
After setting the levels of the signal line and the ACK signal line to valid levels, exchange is required to return them to invalid levels. For this reason, as shown in FIGS. 4 and 5, in each data transfer cycle, "the master side sets the DS fist signal line to a valid level" and "the slave side sets the ACK umbrella signal line to a valid level". 65'', ``Return the DS-signal line to invalid level on the master side 69'', and ``Return the ACK signal line to invalid level on the slave side 7.2'', the control signal makes two round trips between the master and slave. are doing.

In the transmission of signals between master and slave, there are propagation delays55 such as propagation delays caused by passing through bus driver elements and bus receiver elements, and propagation delays of electrical signals on the bus6. An increase in the number of transmissions of control signals results in an increase in data transfer cycle time, which reduces the transmission speed.

An object of the present invention is to minimize the transmission of control signals such as DS signals and ACK signals during data transfer cycles of write or read in data transfer between the master side and slave side connected by the asynchronous data transfer bus. The aim is to improve the data transfer speed.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a control signal line when data is transferred between a master and a slave connected by an asynchronous data transfer bus by executing one or more data transfer cycles. Rather than defining the meaning of valid or invalid for each level, the meaning of valid is defined for each inversion of the level of the control signal line. That is, in a certain data transfer cycle, when the signal level of the DS signal line is inverted from high to low or low to high, the slave side determines that the DSS signal is enabled and enabled on the master side, and similarly, the ACK signal is When the signal level of the line is reversed, the master side will switch to AC on the slave side.
It is determined that the K signal is set to be valid.

(Function) In each data transfer cycle, for example, if a control method is adopted in which the side of the master/slave that writes data to the bus sends a control signal first, the write side writes data to the bus and then controls the control signal. Inverts the level of the signal line.On the read side.

After confirming that the level of the control signal line from the other party has been reversed.

Reads data from the bus and inverts the level of the control signal line. That is, in the case of a write cycle, the master side inverts the level on the DS signal line after writing data to the bus;

On the slave side, after reading data from the bus, the level of the ACK signal line is inverted. In addition, in a read cycle, after writing data to the bus on the slave side,
The level on the CK signal line is inverted, whereas on the master side, after reading data from the bus, the level on the DS signal line is inverted.

After one data transfer cycle ends, if there is more data to transfer, the next data transfer cycle begins.

At this time, the read side knows that it is ready to enter the next cycle when it receives the level inversion of the control signal line from the read side in the previous cycle, so the write side especially checks the signal. Start writing data to the bus without

According to this method, in each data transfer cycle, the DS
Since there is no exchange of signals to disable control signals such as signals and ACK signals, "level inversion of the DS signal line on the master side" + "level inversion of the ACK signal line on the slave side" or "level inversion of the ACK signal line on the slave side""The level of the ACK signal line is inverted on the master side" and the level of the DS signal line is inverted on the master side.

The control signal only makes one round trip between the master and slave.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the configuration of an asynchronous data transfer bus in an embodiment of the present invention. In FIG. 1, the asynchronous data transfer bus 46 has an address strobe signal line 3 for instructing the master side 1 to the slave 2 to complete address setting and start and end data transfer, and a transfer start address. a plurality of address signal lines 4 for giving instructions;
It has a write signal line 5 that instructs the direction of data transfer, and a DS signal line 6 that instructs the start of data transfer for each data transfer cycle. It has an ACK signal line 7 for instructing the completion of data transfer for each cycle, and furthermore, from the master side 1 to the slave side 2 in a write cycle, and from the slave side 2 to the master side 1 in a read cycle.

A plurality of data signal lines 8 are provided for transmitting data contents in each transfer cycle. Of these signal lines, the address strobe signal line 3 and the write signal line 5 are defined as valid when they are at a low level, and are hereinafter referred to as AS* signal lines.

It is written as WR* signal. The exchange of signals between the master and slave according to the present invention will be explained below using the asynchronous data transfer bus shown in FIG.

Figure 2 shows the write data transfer cycle repeated three times.
3 is a timing chart when data is transferred from the master side 1 to the slave side 2. FIG.

First, the start address of data transfer is written from the master side 1 to the address signal line 4 (11), and the As umbrella signal line 3 is set to a low level (12), which is the effective level, thereby starting the data transfer to the slave side 2. By instructing the address and instructing the start of data transfer (13), at the same time, setting the WR fist signal line 5 to a low level, which is the level instructing the write cycle (14),
The slave side 2 is instructed that the data transfer direction of this data transfer is write (15).

Thereafter, a first write cycle 40, which is the first data transfer cycle, begins.

In the first write cycle 40, the master side 1 writes transfer data to the data signal 8a (16). For example, if the initial level of the DS signal line 6 is high, the DS signal line 6
Invert the level from high level to low level (17
), if the initial level is low level, it is inverted to high level.

This instructs the slave side 2 to start data transfer (18), and after passing through the propagation delay 19 on the bus,
When the level inversion (17) is transmitted to the slave side 2, the slave side 2 starts reading data 20) from the data signal line 8a.

After reading is completed, for example, if the initial level of the ACK signal line 7 is high, the level of the ACK signal line 7 is inverted from high level to low level (21).

Note that if the initial level is low level, it is inverted to high level. Via propagation delay 23 on the bus.

When the level inversion (21) of the ACK signal line 7 is transmitted.

The master side 1 finishes writing the transfer data to the data signal 8a (24). At this point, it can be confirmed that the slave side 2 has received the start address, so the start address is transferred to the address signal line 4. Writing ends (2
5), then the second data transfer cycle, the second
Entering write cycle 41, first write cycle 4
Similarly to 0, writing of transfer data to the data signal line 8a is started.

Thereafter, each write cycle continues in the same way, and in the third write cycle 42, when the master side 1 receives the level inversion (27) of the ACK signal line 7 from the slave side 2, the master side 1 sends the AS The signal line 3 is set to a high level, which is an invalid level (28), and an instruction is given to the slave side 2 to end the data transfer.

FIG. 3 is a timing chart when the read data transfer cycle is repeated three times and data is transferred from the slave $1 to the master side 2.

Same as for write data transfer cycles.

First, write the start address to the bus from master side 1 (
11), AS skewer signal line 3 low level setting (12), W
In each subsequent transfer cycle 43, 44, 45, in which the high level setting (13) of the R signal line 5 is performed, the same process is performed between the master side 1 and the slave ([2), except that the relationship between Exchanges control signals.

In the third read cycle, after the master side 1 inverts the level (30) on the DS signal line 6 to the slave side 2, the master side 1 sets the AS signal line 3 to a high level, which is an invalid level (31). ), instructs slave side 2 to end the data transfer (32), and on slave side 2,
After detecting that the AS* signal line 3 is at an invalid level, no new data is written to the bus and the primary transfer cycle does not begin.

〔Effect of the invention〕

As explained above, in the asynchronous data transfer method of the present invention, there is no need for a round trip of a signal to return the level on the control signal line to an invalid level, and the exchange of control signals between the master and slave in each data transfer cycle is Only one round trip is required, which is the minimum required, and the data transfer cycle time for one round trip is shortened compared to the conventional method, so an overall improvement in data transfer speed can be expected.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of an asynchronous data transfer bus in an embodiment of the present invention, FIGS. 2 and 3 are timing charts for explaining an example of the operation of the method of the present invention, and FIGS. The figure is a timing chart for explaining an example of the operation of the conventional system. 1...Master side, 2...Slave side. 3...AS-signal line, 4...Address signal line, 5
...WR signal line, 6...DS signal line, 7...A
CK signal line, 8... data signal line, 46... asynchronous data transfer path.

Claims (1)

[Claims] (1) In a method in which data is transferred by exchanging control signals between a master side and a slave side connected by an asynchronous data transfer bus, each time the signal level of the control signal line is inverted between the master side and slave side. An asynchronous data transfer method characterized by exchanging control signals by defining the meaning of valid.