JPH0227835B2 - - Google Patents

Info

Publication number
JPH0227835B2
JPH0227835B2 JP56171412A JP17141281A JPH0227835B2 JP H0227835 B2 JPH0227835 B2 JP H0227835B2 JP 56171412 A JP56171412 A JP 56171412A JP 17141281 A JP17141281 A JP 17141281A JP H0227835 B2 JPH0227835 B2 JP H0227835B2
Authority
JP
Japan
Prior art keywords
wiring
wiring board
thick film
thin film
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56171412A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5873193A (ja
Inventor
Akira Murata
Kazuyuki Fujimoto
Tsuneaki Kamei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP17141281A priority Critical patent/JPS5873193A/ja
Publication of JPS5873193A publication Critical patent/JPS5873193A/ja
Publication of JPH0227835B2 publication Critical patent/JPH0227835B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP17141281A 1981-10-28 1981-10-28 多層配線基板の製造方法 Granted JPS5873193A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17141281A JPS5873193A (ja) 1981-10-28 1981-10-28 多層配線基板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17141281A JPS5873193A (ja) 1981-10-28 1981-10-28 多層配線基板の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP3105533A Division JPH0810792B2 (ja) 1991-05-10 1991-05-10 多層配線基板の製造方法

Publications (2)

Publication Number Publication Date
JPS5873193A JPS5873193A (ja) 1983-05-02
JPH0227835B2 true JPH0227835B2 (enrdf_load_stackoverflow) 1990-06-20

Family

ID=15922654

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17141281A Granted JPS5873193A (ja) 1981-10-28 1981-10-28 多層配線基板の製造方法

Country Status (1)

Country Link
JP (1) JPS5873193A (enrdf_load_stackoverflow)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6010698A (ja) * 1983-06-29 1985-01-19 日本電気株式会社 多層配線基板およびその製造方法
JPS60170294A (ja) * 1984-02-14 1985-09-03 日本電気株式会社 ピン付き多層配線基板の製造方法
JPS62119951A (ja) * 1985-11-19 1987-06-01 Nec Corp 多層配線基板
JPS63144598A (ja) * 1986-12-09 1988-06-16 日本電気株式会社 多層回路基板
JPS63169797A (ja) * 1987-01-07 1988-07-13 日本電気株式会社 混成集積回路装置
JP2588549B2 (ja) * 1987-11-20 1997-03-05 株式会社日立製作所 半導体装置
JP3087899B2 (ja) * 1989-06-16 2000-09-11 株式会社日立製作所 厚膜薄膜混成多層配線基板の製造方法
JPH0821648B2 (ja) * 1989-06-20 1996-03-04 三菱マテリアル株式会社 厚膜技術により形成されたピンレスグリッドアレイ電極構造

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5328266A (en) * 1976-08-13 1978-03-16 Fujitsu Ltd Method of producing multilayer ceramic substrate

Also Published As

Publication number Publication date
JPS5873193A (ja) 1983-05-02

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