JPH02249249A - 電極接続方法 - Google Patents

電極接続方法

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Publication number
JPH02249249A
JPH02249249A JP1070858A JP7085889A JPH02249249A JP H02249249 A JPH02249249 A JP H02249249A JP 1070858 A JP1070858 A JP 1070858A JP 7085889 A JP7085889 A JP 7085889A JP H02249249 A JPH02249249 A JP H02249249A
Authority
JP
Japan
Prior art keywords
connection
electrode
connection electrodes
substrate
small holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1070858A
Other languages
English (en)
Inventor
Hikari Fujita
光 藤田
Sakae Noda
野田　栄
Matsuki Baba
末喜 馬場
Yoshiro Maki
牧　芳郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1070858A priority Critical patent/JPH02249249A/ja
Publication of JPH02249249A publication Critical patent/JPH02249249A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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  • Engineering & Computer Science (AREA)
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、電極パターンを有する基板と接続電極を有す
る素子の電極接続方法に関する。
従来の技術 従来、接続電極を有する素子と電極パターンを有する基
板との間の電極接続方法として、ワイヤーボンディング
方法が一般に採用されている。このワイヤーボンディン
グ方法としては、第３図に示すように電極パターン２を
有する基板１上に導電性接着樹脂６ｂなどにより接続電
極４を有する素子７をグイボンド後、基板加熱状態にお
いて基板１上の電極パターン２と接続電極４間をＡｕ線
等の導体９により超音波圧接接続する方法があった。こ
の際、接続電極４は、薄膜の場合が多く１μｍ以上の厚
みが必要であり密着力が大きくなければならなかった。
さらに、接続に用いる導体９は、バネ弾性力を何しない
金属材料が用いられていた。
発明が解決しようとする課題 しかし、前述の従来技術では、以下に示すような課題を
有する。
従来のワイヤーボンディング方法を用いた電極接続方法
では、接続時、加熱や超音波エネルギーと大きい荷重（
１０ｇ以上）の加圧力が必要とされ、素子に対するスト
レスが大きく、素子の電気的特性が劣化する可能性が大
きかった。
さらに、接続電極と素子との密着力が小さい場合、これ
に左右されて導体と素子との電気的接続が不安定になる
という問題があった。
本発明は、上記問題点を解消するため新規な電極接続方
法を提供することを目的とする。
課題を解決するための手段 上記課題を解決するため、本発明は、素子上の接続電極
と基板上の電極パターンとを導体を用いて固着と電気的
接続を行なう接続方法において、前記素子の接続電極部
に小孔を設け、前記導体を前記接続電極部の小孔近傍に
導電性接着樹脂を介して固着と電気的接続を行なうこと
を特徴とする電極接続方法である。
前記導体はバネ弾性力を有することが好ましく、この導
体を接続電極部の小孔近傍にバネ弾性力により圧接させ
た状態で、導電性接着樹脂を介して偏着と電気的接続を
行うとよい。
作　　　用 上記のように、素子の接続電極上に小孔を設けているた
め、接続電極の密着力が弱い場合でも、小孔部分におい
て素子と導体を導電性接着樹脂が直接接着し保持する。
このため接続電極の密着力に左右されない強い接着力で
安定した固着と電気的接続が素子と導体との間で得られ
る。このとき、小孔の大きさを変えることにより自由に
接着力を変えることも可能である。
さらに、導体としてバネ弾性力を有しているものを用い
ると、導電性接着樹脂を塗布するとき接続電極面に常に
接触し安定した接続が得られる。
このとき、導体の断面積は、一般に数！００μｍＱと小
面積のためバネ弾性力も小さく、接続時の加重を数ｇと
小さくできるとともに素子に対して低ストレスで安定し
た接続が可能となり高信頼性の電気的接続が得られる。
実施例 以下に本発明の一実施例を図面に基づいて説明する。
第１図は、本実施例において接続電極４を存する素子７
と電極パターン２ををする基板１との接合状態を示すも
のである。そして１個の小孔３を設けた接続電極４を有
する素子７に、バネ弾性力を有した導体５の一端部を導
電性接着樹脂６ａを介して固着と電気的接続を行ってい
る。第２図は、第１図の素子７の部分図である。
本実施例では第１図に示すように、例えば、ＡＵやＡ１
等で形成された電極パターン２を有するガラス基板やア
ルミナ基板などの基板１上に、ＡＵやｐｔ等で形成した
接続電極４に小孔３を設けた素子７を導電性接着樹脂θ
ｂなどによりグイボンドする。この後、例えば、絶縁物
８で保持したバネ弾性力を有しＡｕメツキしたリン青銅
の導体５を接続電極４の小孔３近傍にバネ弾性力を用い
て圧接させる。この状態において導電性接着樹脂８ａを
適量塗布し硬化させ固着と電気的接続を得る。
この方法によれば、接続電極４上の小孔３の形状は丸、
四角においても可能であり、その個数、面積を変えるこ
とにより接着力のコントロールも可能となる。また、電
極パターン２の接続においても前記電極接続方法の応用
が容易に考えられる。
さらに、導体５は、形状記憶合金などを用いることによ
り一定加重とすることもできる。
発明の詳細 な説明したように本発明によれば、接続電極を有する素
子の接続電極に小孔を設け、導体の接続を導電性接着樹
脂層を介して固着と電気的接合を得るため従来に比べ強
く安定した接着力が得られる。
さらに、導体をバネ弾性力を存するものとすれば、接続
時の大きな加重と超音波エネルギーを必要とせず、素子
は低ストレスで安定した接続が得られるため導電性接着
樹脂を硬化した後も抵抗値の安定した特性劣化の無い信
頼性の高い電気的接続を得ることが出来る。
【図面の簡単な説明】
第１図は本発明の一実施例における電極接続方法を適用
した基板と素子の斜視図、第２図は第１図における素子
の斜視図、第３図は従来の電極接読方法を適用した基板
と素子の斜視図である。 １・・基板、２・・電極パターン、３・・小孔、４・・
接続電極、５・・導体、６ｂ・・導電性接着樹脂、７・
・素子。 代理人の氏名　弁理士　粟野重孝　はか１名′／系子

Claims (2)

    【特許請求の範囲】
  1. （１）素子上の接続電極と基板上の電極パターンとを導
    体を用いて固着と電気的接続を行なう接続方法において
    、前記素子の接続電極部に小孔を設け、前記導体を前記
    接続電極部の小孔近傍に導電性接着樹脂を介して固着と
    電気的接続を行うことを特徴とする電極接続方法。
  2. （２）導体はバネ弾性力を有し、この導体を接続電極部
    の小孔近傍にバネ弾性力により圧接させた状態で、導電
    性接着樹脂を介して固着と電気的接続を行うことを特徴
    とする請求項１記載の電極接続方法。
JP1070858A 1989-03-23 1989-03-23 電極接続方法 Pending JPH02249249A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1070858A JPH02249249A (ja) 1989-03-23 1989-03-23 電極接続方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1070858A JPH02249249A (ja) 1989-03-23 1989-03-23 電極接続方法

Publications (1)

Publication Number Publication Date
JPH02249249A true JPH02249249A (ja) 1990-10-05

Family

ID=13443682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1070858A Pending JPH02249249A (ja) 1989-03-23 1989-03-23 電極接続方法

Country Status (1)

Country Link
JP (1) JPH02249249A (ja)

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